STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet - Page 9

• Manufacturer Part Number: STPC4EDBC
• Description: X86 Core PC Compatible Information Appliance System-on-Chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

1.8. CLOCK TREE
The STPC Atlas integrates many features and
generates all its clocks from a single 14MHz
oscillator. This results in multiple clock domains as
described in
DEVCLK
(24MHz)
CRTC,Video,TV
Figure
VIP
XTALO
1-2.
14.31818 MHz
DEVCLK
VCLK
PLL
Figure 1-2. STPC Consumer-II clock architecture
XTALI
DCLK
Release 1.5 - January 29, 2002
DCLK
PLL
OSC14M
(14MHz)
IPC
ISA
South Bridge
MCLKO
The speed of the PLLs is either fixed (DEVCLK),
either programmable by strap option (HCLK)
either programmable by software (DCLK, MCLK).
When in synchronized mode, MCLK speed is fixed
to HCLKO speed and HCLKI is generated from
MCLKI.
1/2
ISACLK
MCLK
PLL
1/4
PCICLKI
CPU
North Bridge
MCLKI
Local Bus
HCLK
GENERAL DESCRIPTION
Host
PLL
SDRAM controller
1/2
1/3
x1
x2
PCICLKO
HCLKO
GE
HCLKI
HCLK
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