STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet - Page 38

• Manufacturer Part Number: STPC4EDBC
• Description: X86 Core PC Compatible Information Appliance System-on-Chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ELECTRICAL SPECIFICATIONS
4.5.1. POWER ON SEQUENCE
Figure 4-3
the STPC, also called cold reset.
There is no dependency between the different
power supplies and there is no constraint on their
rising time.
SYSRSTI# as no constraint on its rising edge but
must stay active until power supplies are all within
specifications, a
recommended to let the STPC PLLs and strap
options stabilize.
38/93
Strap Options
Power Supplies
14 M Hz
SYSRSTI#
ISACLK
HCLK
PCI_CLK
SYSRSTO#
describes the power-on sequence of
margin
of
Figure 4-3. Power-on timing diagram
10 s
Release 1.5 - January 29, 2002
is
even
> 10 us
VALID CONFIGURATION
1.6 V
Strap Options are continuously sampled during
SYSRSTI# low and must remain stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# goes high.
Bus activity starts only few clock cycles after the
release of SYSRSTO#. The toggling signals
depend on the STPC configuration.
In ISA mode, activity is visible on PCI prior to the
ISA bus as the controller is part of the south
bridge.
In Local Bus mode, the PCI bus is not accessed
and the Flash Chip Select is the control signal to
monitor.
2.3 m s