STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet - Page 43
STPC4EDBC
Manufacturer Part Number
STPC4EDBC
Description
X86 Core PC Compatible Information Appliance System-on-Chip
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.STPC4EDBC.pdf
(93 pages)
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4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS
Table 4-7
tics of the ISA interface.
Figure 4-7 ISA Cycle (ref
Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
The clock has not been represented as it is dependent on the ISA Slave mode.
Note: The signal numbering refers to
Name
10
10
2
3
9
CONTROL (Note 1)
and
WRITE DATA
READ DATA
Parameter
LA[23:17] valid before ALE# negated
LA[23:17] valid before MEMR#, MEMW# asserted
SA[19:0] & SBHE valid before ALE# negated
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
LA [23:17]
IOCHRDY
SA [19:0]
IOCS16#
Table 4-13
MCS16#
10a Memory access to 16-bit ISA Slave
10b Memory access to 8-bit ISA Slave
10c Memory access to 16-bit ISA Slave
AEN
3a Memory access to 16-bit ISA Slave
3b Memory access to 8-bit ISA Slave
ALE
Valid Address
list the AC characteris-
Table
2
4-13)
Valid AENx
Table 4-7
3
Table 4-13. ISA Bus AC Timing
12
12
Release 1.5 - January 29, 2002
13
9
10
14
18
33
22
61
34
Valid Address, SBHE*
37
41
38
47
15
11
42
48
23
23
25
24
VALID DATA
ELECTRICAL SPECIFICATIONS
26
26
Min
5T
5T
5T
1T
2T
2T
2T
55
56
54
V.Data
57
29
58
59
27
64
Max
28
28
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Units
Cycle
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