ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 9

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

4.2.5
4.2.6
4.2.7
4.2.7.1
4680C–4BMCU–01/05
I/O Bus
Instruction Set
Interrupt Structure
Interrupt Processing
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication
between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O
control. With the MARC4 IN and OUT instructions the I/O bus allows a direct read or write
access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip periph-
erals is described in the section “Peripheral Modules”. The I/O bus is internal and is not
accessible by the customer on the final microcontroller device, but it is used as the interface for
the MARC4 emulation (see section “Emulation”).
The MARC4 instruction set is optimized for the high level programming language qFORTH.
Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and
compact program code. The CPU has an instruction pipeline allowing the controller to prefetch
an instruction from program memory at the same time as the present instruction is being exe-
cuted. The MARC4 is a zero address machine, the instructions containing only the operation to
be performed and no source or destination address fields. The operations are implicitly per-
formed on the data placed on the stack. There are one and two byte instructions which are
executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock
cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single
machine cycle. For more information refer to the “MARC4 Programmer's Guide”.
The MARC4 can handle interrupts with eight different priority levels. They can be generated
from the internal and external interrupt sources or by a software interrupt from the CPU itself.
Each interrupt level has a hard-wired priority and an associated vector for the service routine in
the program memory (see
of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still
be registered, but the interrupt routine only started after the I flag is set. All interrupts can be
masked, and the priority individually software configured by programming the appropriate control
register of the interrupting module (see section “Peripheral Modules”).
For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two
8-bit wide “interrupt pending” and “interrupt active” registers. The interrupt controller samples all
interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pend-
ing register. If no higher priority interrupt is present in the interrupt active register, it signals the
CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor
enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the
service routine is executed and the current PC is saved on the return stack.
An interrupt service routine is completed with the RTI instruction. This instruction resets the cor-
responding bits in the interrupt pending/active register and fetches the return address from the
return stack to the program counter. When the interrupt enable flag is reset (triggering of inter-
rupt routines are disabled), the execution of new interrupt service routines is inhibited but not the
logging of the interrupt requests in the interrupt pending register. The execution of the interrupt
is delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an inter-
rupt request occurs while the corresponding bit in the pending register is still set (i.e., the
interrupt service routine is not yet finished).
Table 4-2 on page
11). The programmer can postpone the processing
ATAM893-D
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