ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 69

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ATAM893X-TKHYZ

Manufacturer Part Number
ATAM893X-TKHYZ
Description
Flash Version for ATAR080, ATAR090/890 and ATAR092/892
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
5.3.4.11
5.3.4.12
4680C–4BMCU–01/05
Serial Interface Registers
Serial Interface Control Register 1 (SIC1)
Table 5-16.
SIC1
SIR
SCD
Note:
SCS1
SCS0
Note:
• In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded
• Setting SIR bit loads the contents of the shift register into the receive buffer
• In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop
(SRDY = 1).
(synchronous 8-bit mode only).
condition.
SCS1
1
1
0
0
This bit has to be set to '1' during the MCL mode and the Timer 3 mode 10 or 11
With SCD = '0' the bits SCS1 and SCS0 are insignificant
Bit 3
SIR
Serial Interface Reset
SIR = 1, SSI inactive
SIR = 0, SSI active
Serial Clock Direction
SCD = 1, SC line used as output
SCD = 0, SC line used as input
Serial Clock source Select bit 1
Serial Clock source Select bit 0
Serial Clock Source Select Bits
Bit 2
SCD
SCS0
1
0
1
0
Bit 1
SCS1
Internal Clock for SSI
SYSCL/2
T1OUT/2
POUT/2
TOG2/2
Bit 0
SCS0
Auxiliary register address: '9'hex
Reset value: 1111b
ATAM893-D
69

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