ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 11

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

Table 4-2.
4.2.7.3
4.2.7.4
4.3
4680C–4BMCU–01/05
Interrupt
Master Reset
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Software Interrupts
Hardware Interrupts
Hardware Interrupts
The programmer can generate interrupts by using the Software Interrupt Instruction (SWI) which
is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered
interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the
top two elements from the expression stack and writes the corresponding bits via the I/O bus to
the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prior-
itized or lower priority processes scheduled for later execution.
In the ATAM893-D, there are eleven hardware interrupt sources with seven different levels.
Each source can be masked individually by mask bits in the corresponding control registers. An
overview of the possible hardware configurations is shown in
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated
independent of the current program state. It can be triggered by either initial supply power-up, a
short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an exter-
nal input clock supervisor stage (see
A master reset activation will reset the interrupt enable flag, the interrupt pending register and
the interrupt active register. During the power-on reset phase the I/O bus control signals are set
to reset mode thereby initializing all on-chip peripherals. All bi-directional ports are set to input
mode.
Attention: During any reset phase, the BP20/NTE input is driven towards V
up transistor. This pin must not be pulled down to V
resenting a resistor of less than 150 k .
Releasing the reset results in a short call instruction (opcode C1h) to the EEPROM address
008h. This activates the initialization routine $RESET which in turn has to initialize all necessary
RAM variables, stack pointers and peripheral configuration registers (see
Register
T3CM1
T3CM2
P5CR
T2CM
P5CR
SISC
VCM
T1M
T3C
Interrupt Mask
P52M1, P52M2
P53M1, P53M2
P50M1, P50M2
P51M1, P51M2
T3EIM
T3IM1
T3IM2
T1IM
T2IM
SIM
VIM
Bit
Figure 4-7 on page
Interrupt Source
Any edge at BP52
Any edge at BP53
Timer 1
SSI buffer full/empty or BP40/BP43 interrupt
Timer 2 compare match/overflow
Timer 3 compare register 1 match
Timer 3 compare register 2 match
Timer 3 edge event occurs (T3I)
Any edge at BP50
Any edge at BP51
External/internal voltage monitoring
SS
during reset by any external circuitry rep-
12).
Table
4-2.
Table 5-1 on page
ATAM893-D
DD
by a strong pull-
23).
11