CY8C20111_12 CYPRESS [Cypress Semiconductor], CY8C20111_12 Datasheet - Page 8

• Manufacturer Part Number: CY8C20111_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Operating Modes
Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The timings remain approximately the same for
different
acknowledgment times in normal mode, the registers 0x07,
0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D are given only read access.
Writing to these registers can be done only in setup mode.
Setup Mode
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
Table 1. I
I
“Clock stretching” or “bus stalling” in I
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait
until the SCL is released by the slave.
When an I
device, the CapSense Express stalls the I
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I
with the CapSense Express device.
Document Number: 001-53516 Rev. *H
2
C Clock Stretching
7-bit Slave Address (in
2
2
configurations
C master communicates with the CapSense Express
C Addresses
Dec)
75
75
1
1
2
C compliant master to communicate
of
the
D7
0
0
1
1
2
slave.
C communication protocol
D6
0
0
0
0
Figure 8. Write ACK Time Representation
2
To
C bus after the
reduce
D5
0
0
0
0
D4
the
0
0
1
1
I
The CapSense Express devices support the industry standard
I
■
■
■
■
The I
I
The device uses a seven bit addressing protocol. The I
transfer is always initiated by the master sending one byte
address; first 7-bit contains address and LSb indicates the data
transfer direction. Zero in the LSb indicates the write transaction
form master and one indicates read transfer by the master.
Table 3
An I
banged software I
time specified (as shown in the section
and
next bit is transmitted. It is mandatory to check the SCL status (it
should be high) before I
CapSense Express. If the master fails to do so and continues to
communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
the
D3
2
2
2
0
0
0
0
C protocol, which can be used to:
C Device Addressing
Configure the device
Read the status and data registers of the device
Control device operation
Execute commands
C Interface
Register Map
2
Read) for each register write and read operation before the
2
C master which does not support clock stretching (a bit
C address can be modified during configuration.
shows example for different I
D2
0
0
1
1
on page 7.
2
D1
1
1
1
1
C Master) must wait for a specific amount of
CY8C20111, CY8C20121
2
C master initiates any data transfer with
0(W)
0(W)
1(W)
1(R)
D0
8-bit Slave Address (in
2
C addresses.
Format for Register Write
Hex)
02
03
96
97
Page 8 of 44
2
C data