CY8C20111_12 CYPRESS [Cypress Semiconductor], CY8C20111_12 Datasheet - Page 40

• Manufacturer Part Number: CY8C20111_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Glossary
Document Number: 001-53516 Rev. *H
cyclic redundancy
check (CRC)
data bus
debugger
dead band
digital blocks
digital-to-analog
(DAC)
duty cycle
emulator
External Reset
(XRES)
Flash
Flash block
frequency
gain
I
ICE
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
interrupt service
routine (ISR)
jitter
2
C
(continued)
A suspension of a process, such as the execution of a computer program, caused by an event external to that
A calculation used to detect errors in data communications, typically performed using a linear feedback shift
register. Similar calculations may be used for a variety of other purposes such as data compression.
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
A period of time when neither of two or more signals are in their active state or in transition.
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse operation.
The relationship of a clock period high time to its low time, expressed as a percent.
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
process, and performed in such a way that the process can be resumed.
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
serial data streams.
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
CY8C20111, CY8C20121
Page 40 of 44