XC5204 XILINX [Xilinx, Inc], XC5204 Datasheet - Page 39

• Manufacturer Part Number: XC5204
• Description: Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Notes: 1. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are high.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 36: Asynchronous Peripheral Mode Programming Switching Characteristics
November 5, 1998 (Version 5.2)
RDY/BUSY
WS/CS0
RS, CS1
D0-D7
DOUT
CCLK
Write
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
3. CCLK and DOUT timing is tested in slave mode.
4. T
RDY
and the phase of internal timing generator for CCLK.
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
loaded into the input register before the second-level buffer has started shifting out data.
BUSY
R
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T
Effective Write time
(CSO, WS=Low; RS, CS1=High
DIN setup time
DIN hold time
RDY/BUSY delay after end of
Write or Read
RDY/BUSY active after beginning
of Read
RDY/BUSY Low output (Note 4)
Write to LCA
1 T
T
CA
WTRB
Description
2 T
DC
4
Previous Byte D6
3 T
CD
XC5200 Series Field Programmable Gate Arrays
1
2
3
4
7
6
6 T
Symbol
BUSY
T
T
T
T
T
WTRB
BUSY
DC
CD
CA
D7
7
Min
100
60
0
2
BUSY
D0
Read Status
occurs when a new word is
READY
BUSY
D1
Max
60
60
9
4
D2
periods
CCLK
Units
BUSY
RS, CS0
WS, CS1
D7
ns
ns
ns
ns
ns
X6097
7-121
7