XC5204 XILINX [Xilinx, Inc], XC5204 Datasheet
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XC5204
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XC5204 Summary of contents
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... PC platforms. Popular design entry methods are fully supported, including ABEL, sche- matic capture, VHDL, and Verilog HDL synthesis. Design- ers utilizing logic synthesis can use their existing tools to design with the XC5200 devices. . XC5204 XC5206 256 480 784 3,000 ...
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XC5200 Series Field Programmable Gate Arrays XC5200 Family Compared to XC4000/Spartan™ and XC3000 Series For readers already familiar with the XC4000/Spartan and XC3000 FPGA Families, this section describes significant differences between them and the XC5200 family. Unless otherwise indicated, comparisons ...
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R XC3000 family: XC5200 devices support an additional pro- gramming mode: Peripheral Synchronous. XC3000 family: The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any flip-flops. XC3000 family: The XC5200 family does ...
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XC5200 Series Field Programmable Gate Arrays The XC5200 CLB consists of four LCs, as shown in Figure 4. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs can be configured to implement ...
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R single-length lines, double-length lines, and Longlines all routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained Versa-Block. Throughout the XC5200 interconnect, an effi- cient multiplexing scheme, in combination with three layer metal (TLM), was used ...
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XC5200 Series Field Programmable Gate Arrays carry out CY_MUX and B3 XOR F2 to any two CY_MUX and B2 XOR F2 to any two ...
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R tomized RPMs, freeing the designer from the need to become an expert on architectures. cascade out CO DI CY_MUX A15 F4 A14 F3 AND A13 F2 A12 F1 DI CY_MUX F4 A11 F3 A10 AND ...
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XC5200 Series Field Programmable Gate Arrays can also be independently disabled for any flip-flop. CLR is active High not invertible within the CLB. PAD IBUF Figure 8: Schematic Symbols for Global Reset Global Reset A separate Global Reset ...
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R ~100 k "Weak Keeper" Figure 10: 3-State Buffers Implement a Multiplexer Input/Output Blocks User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con- figured ...
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XC5200 Series Field Programmable Gate Arrays non-zero hold, attach a NODELAY attribute or property to the flip-flop or input buffer. IOB Output Signals Output signals can be optionally inverted within the IOB, and pass directly to the pad. As with ...
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R to Vcc. The configurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors value makes them unsuitable as wired-AND pull-up resis- tors. The pull-up resistors for most user-programmable IOBs are ...
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XC5200 Series Field Programmable Gate Arrays 4 Global Nets 4 North South 4 East 4 West 4 Multiplexers Direct North 4 Feedback 4 Direct West 4 4 Direct South Figure 14: VersaBlock Details CLB inputs have several possible sources: the ...
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R Matrix through a hierarchy of different-length metal seg- ments in both the horizontal and vertical directions. A pro- GRM Versa- Block GRM Versa- Block GRM Versa- Block Six Levels of Routing Hierarchy 1 Single-length Lines 2 Double-length Lines 3 ...
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XC5200 Series Field Programmable Gate Arrays segments span the width and height of the chip, respectively. Two low-skew horizontal and vertical unidirectional glo- bal-line segments span each row and column of the chip, respectively. Single- and Double-Length Lines The single- ...
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R . Figure 17: Detail of Programmable Interconnect Associated with XC5200 Series CLB November 5, 1998 (Version 5.2) XC5200 Series Field Programmable Gate Arrays 7 7-97 ...
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XC5200 Series Field Programmable Gate Arrays VersaRing Input/Output Interface The VersaRing, shown in Figure 18, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without the CLB logic. The Ver- ...
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R senting the decoding of the corresponding state of the boundary-scan internal state machine. IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI M U INSTRUCTION REGISTER TDO X BYPASS REGISTER IOB ...
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XC5200 Series Field Programmable Gate Arrays XC5200-Series devices can also be configured through the boundary scan logic. See XAPP 017 for more information. Data Registers The primary data register is the boundary scan register. For each IOB pin in the ...
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R Optional IBUF BSCAN RESET UPDATE SHIFT TDI TDO TMS DRCK TCK IDLE TDO1 SEL1 From User Logic TDO2 SEL2 Figure 20: Boundary Scan Schematic Example Even if the boundary scan symbol is used in a schematic, the input pins ...
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XC5200 Series Field Programmable Gate Arrays tions During Configuration” on page tion Timing” section. Table 9: Pin Descriptions I/O I/O During After Pin Name Config. Config. Permanently Dedicated Pins Five or more (depending on package) connections to the nominal +5 ...
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R Table 9: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing ...
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XC5200 Series Field Programmable Gate Arrays Table 9: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration is completed. Weak I/O I/O ...
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R Master Serial mode generates CCLK and receives the con- figuration data in serial form from a Xilinx serial-configura- tion PROM. CCLK speed is selectable as 1 MHz (default), 6 MHz MHz. Configuration always starts at the default ...
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XC5200 Series Field Programmable Gate Arrays Reset Active Low Output 1 1 Active High Output etc . . . . Figure 22: CCLK Generation for XC3000 Master Driving an XC5200-Series Slave Express ...
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... Once per data frame Table 12: Internal Configuration Data Structure VersaBlock Device Once per de- vice XC5202 Once per bit- XC5204 stream XC5206 XC5210 XC5215 Bits per Frame = (34 x number of Rows for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill ...
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XC5200 Series Field Programmable Gate Arrays Polynomial: X16 + X15 + ...
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R Length Count Match CCLK DONE I/O XC2000 Global Reset DONE XC3000 I/O Global Reset DONE I/O XC4000E/EX XC5200/ CCLK_NOSYNC GSR Active DONE IN DONE C1 I/O XC4000E/EX XC5200/ CCLK_SYNC GSR Active DONE I/O XC4000E/EX XC5200/ UCLK_NOSYNC ...
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XC5200 Series Field Programmable Gate Arrays Configuration The length counter begins counting immediately upon entry into the configuration state. In slave-mode operation it is important to wait at least two cycles of the internal 1-MHz clock oscillator after INIT is ...
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R When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used ...
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XC5200 Series Field Programmable Gate Arrays DONE High to active user I/O is controlled by an option to the bitstream generation software. Q3 Q1/Q4 STARTUP DONE FULL S ...
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R Note that in XC5200-Series devices, configuration data is not inverted with respect to configuration XC2000 and XC3000 families. Readback of Express mode bitstreams results in data that does not resemble the original bitstream, because the ...
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XC5200 Series Field Programmable Gate Arrays Configuration Timing The seven configuration modes are discussed in detail in this section. Timing specifications are included. Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input of the FPGA. ...
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R Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. ...
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XC5200 Series Field Programmable Gate Arrays HIGH or 3.3 K LOW M0 M1 DOUT NOTE:M0 can be shorted to Ground if not used as I/O. XC5200 VCC Master Parallel 4.7K INIT PROGRAM ...
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R . A0-A17 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description Delay to Address valid CCLK Data setup time Data hold time Note power-up, V must rise from 2 Low until V is ...
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XC5200 Series Field Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configura- tion data must be available ...
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R T CCL CCLK INIT BYTE DOUT RDY/BUSY Description INIT (High) setup time setup time hold time CCLK CCLK High time CCLK Low time CCLK Frequency Notes: ...
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XC5200 Series Field Programmable Gate Arrays Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept byte-wide data ...
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R Write to LCA WS/CS0 RS, CS1 D0-D7 CCLK 4 T WTRB RDY/BUSY DOUT Description Effective Write time (CSO, WS=Low; RS, CS1=High Write DIN setup time DIN hold time RDY/BUSY delay after end of ...
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XC5200 Series Field Programmable Gate Arrays Express Mode Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive ...
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R CCLK INIT D0-D7 Serial Data Out (DOUT) RDY/BUSY CS1 Description INIT (High) Setup time required DIN Setup time required DIN hold time required CCLK CCLK High time CCLK Low time CCLK frequency Note: If not driven ...
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XC5200 Series Field Programmable Gate Arrays Table 13. Pin Functions During Configuration CONFIGURATION MODE: <M2:M1:M0> SLAVE MASTER-SER SYN.PERIPH <1:1:1> <0:0:0> <0:1:1> TDI TDI TCK TCK TMS TMS M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) M0 (HIGH) (I) M0 ...
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R Configuration Switching Characteristics T Vcc POR PROGRAM INIT CCLK OUTPUT or INPUT X1532 Master Modes Description Power-On-Reset Program Latency CCLK (output) Delay period (slow) period (fast) Slave and Peripheral Modes Description Power-On-Reset Program Latency CCLK (input) Delay (required) period ...
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XC5200 Series Field Programmable Gate Arrays XC5200 Program Readback Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are ...
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R XC5200 Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or ...
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... Max Symbol Device (ns) (ns) T XC5202 9.1 8.5 BUFG XC5204 9.3 8.7 XC5206 9.4 8.8 XC5210 9.4 8.8 XC5215 10.5 9.9 Speed Grade -6 Max Max Symbol Device (ns) (ns) T XC5202 6.0 3.8 IO XC5204 6.4 4.1 XC5206 6.6 4.2 XC5210 6.6 4.2 XC5215 7.3 4.6 T XC5202 7.8 5.6 ON XC5204 8.3 5.9 XC5206 8.4 6.0 XC5210 8.4 6.0 XC5215 8.9 6.3 T XC52xx 3.0 2.8 OFF November 5, 1998 (Version 5. Max Max (ns) (ns) 8.0 6.9 8.2 7.6 8.3 7.7 8.5 7.7 9.8 9 Max Max (ns) (ns) 3.0 2.0 3.2 2.3 3.3 2.7 3.3 2.9 3.8 3 ...
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R XC5200 CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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... XC5210 . . XC5215 T XC5202 PSUF CLB XC5204 F,DI (Min) XC5206 XC5210 XC5215 T XC5202 PHF CLB XC5204 (Min) F,DI XC5206 XC5210 XC5215 T XC5202 PSU CLB XC5204 DI XC5206 XC5210 XC5215 T XC5202 L PSU CLB XC5204 F (Min) XC5206 XC5210 XC5215 T XC52xx PH CLB F,DI (Min Max Max Max ...
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R XC5200 IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...
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XC5200 Series Field Programmable Gate Arrays XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC5200 devices unless otherwise noted. ...
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R Device-Specific Pinout Tables Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die, and include boundary scan register locations. Pin Locations for XC5202 Devices The following table may contain pinout information for ...
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XC5200 Series Field Programmable Gate Arrays Pin Description VQ64* 35. I/O (HDC) 19 36. I/O - 37. I/O (LDC) 20 GND - 38. I/O - 39. I/O 21 40. I/O - 41. I/O - 42. I/O 22 43. I/O (ERR, ...
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... Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD Pin Locations for XC5204 Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information. ...
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XC5200 Series Field Programmable Gate Arrays Pin Description 14. I/O 15. I/O (A14) 16. I/O (A15) VCC GND 17. GCK1 (A16, I/O) 18. I/O (A17) 19. I/O 20. I/O 21. I/O (TDI) 22. I/O (TCK) GND 23. I/O 24. I/O ...
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R Pin Description 57. I/O 58. I/O 59. I/O 60. I/O 61. I/O 62. I/O 63. I/O (ERR, INIT) VCC GND 64. I/O 65. I/O 66. I/O 67. I/O 68. I/O 69. I/O 70. I/O 71. I/O GND 72. I/O ...
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XC5200 Series Field Programmable Gate Arrays Pin Description 99. I/O 100. I/O 101. I/O GND 102. I/O (D1) 103. I/O (RCLK-BUSY/RDY) 104. I/O 105. I/O 106. I/O (D0, DIN) 107. I/O (DOUT) CCLK VCC 108. I/O (TDO) GND 109. I/O ...
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R Pin Locations for XC5206 Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information. Pin Description PC84 PQ100 VCC ...
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XC5200 Series Field Programmable Gate Arrays Pin Description PC84 42. I/O - 43. I/O 25 44. I/O 26 45. I/O - 46. I/O - GND - 47. I/O - 48. I/O - 49. I/O 27 50. I/O - 51. I/O ...
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R Pin Description PC84 PQ100 87. I/O - 88. I 89. I 90. I/O - 91. I/O - 92. I 93. I GND 52 52 DONE 53 53 VCC 54 54 PROG ...
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XC5200 Series Field Programmable Gate Arrays Pin Description PC84 CCLK 73 VCC 74 130. I/O (TDO) 75 GND 76 131. I/O (A0, WS) 77 132. GCK4 (A1, I/O) 78 133. I/O - 134. I/O - 135. I/O (A2, CS1) 79 ...
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R Pin Description PC84 7. I/O (A10) 8. I/O (A11) VCC 9. I/O 10. I/O 11. I/O 12. I/O GND 13. I/O 14. I/O 15. I/O 16. I/O 17. I/O (A12) 18. I/O (A13) 19. I/O 20. I/O 21. I/O ...
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XC5200 Series Field Programmable Gate Arrays Pin Description 50. I/O 51. I/O 52. I/O 53. I/O 54. I/O 55. I/O 56. I/O VCC 57. I/O 58. I/O 59. I/O 60. I/O GND 61. I/O 62. I/O 63. I/O 64. I/O ...
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R Pin Description PC84 95. I/O 96. I/O 97. I/O 98. I/O 40 99. I/O (ERR, INIT) 41 VCC 42 GND 43 100. I/O 44 101. I/O 45 102. I/O 103. I/O 104. I/O 105. I/O 106. I/O 107. I/O ...
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XC5200 Series Field Programmable Gate Arrays Pin Description 137. I/O 138. I/O 139. I/O VCC 140. I/O (D5) 141. I/O (CS0) 142. I/O 143. I/O 144. I/O 145. I/O 146. I/O (D4) 147. I/O VCC GND 148. I/O (D3) 149. ...
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R Pin Description PC84 180. I/O 181. I/O 182. I/O 183. I/O 184. I/O - GND 185. I/O 186. I/O 187. I/O 188. I/O VCC 189. I/O (A4) 81 190. I/O (A5) 82 191. I/O 192. I/O 193. I/O 194. ...
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XC5200 Series Field Programmable Gate Arrays Pin Description 8. I/O (A11) 9. I/O 10. I/O VCC 11. I/O 12. I/O 13. I/O 14. I/O GND 15. I/O 16. I/O 17. I/O 18. I/O 19. I/O 20. I/O 21. I/O (A12) ...
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R Pin Description PQ160 54. I/O 55. I/O 56. I/O 57. I/O 58. I/O 59. I/O 60. I/O GND VCC 61. I/O 62. I/O 63. I/O 64. I/O 65. I/O 66. I/O 67. I/O 68. I/O 69. I/O 70. I/O ...
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XC5200 Series Field Programmable Gate Arrays Pin Description 100. I/O 101. I/O 102. I/O 103. I/O 104. I/O 105. I/O 106. I/O 107. I/O 108. I/O 109. I/O GND 110. I/O 111. I/O 112. I/O 113. I/O VCC 114. I/O ...
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R Pin Description PQ160 146. I/O 147. I/O 148. I/O 149. I/O 150. I/O 151. I/O 152. I/O 153. I/O GND DONE VCC PROG 154. I/O (D7) 155. GCK3 (I/O) 156. I/O 157. I/O 158. I/O 159. I/O 160. I/O ...
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XC5200 Series Field Programmable Gate Arrays Pin Description 190. I/O 191. I/O 192. I/O (D2) 193. I/O VCC 194. I/O 195. I/O 196. I/O 197. I/O GND 198. I/O 199. I/O 200. I/O 201. I/O 202. I/O 203. I/O 204. ...
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R Pin Description PQ160 235. I/O 236. I/O 237. I/O (A4) 238. I/O (A5) 239. I/O 240. I/O 241. I/O 242. I/O 243. I/O (A6) 244. I/O (A7) GND Additional No Connect (N.C.) Connections for HQ208 and HQ240 Packages HQ208 ...
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... I= Industrial +100 VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only. User I/O Per Package Max Device I/O VQ64 PC84 PQ100 XC5202 XC5204 124 65 81 XC5206 148 65 81 XC5210 196 65 XC5215 244 7/8/98 Ordering Information Example: ...
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R Revisions Version 12/97 Rev 5.0 added -3, -4 specification 7/98 Rev 5.1 added Spartan family to comparison, removed HQ304 11/98 Rev 5.2 All specifications made final. November 5, 1998 (Version 5.2) XC5200 Series Field Programmable Gate Arrays Description 7 ...