XC4VFX20 XILINX [Xilinx, Inc], XC4VFX20 Datasheet - Page 52

• Manufacturer Part Number: XC4VFX20
• Description: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Revision History
The following table shows the revision history for this document.
DS302 (v3.2) April 10, 2008
Product Specification
08/02/04
09/09/04
01/18/05
02/01/05
02/24/05
05/19/05
06/17/05
06/27/05
08/06/05
08/29/05
09/28/05
Date
R
Version
1.10
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Initial Xilinx release. Printed Handbook version.
Edits in Tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. Removed Table 39.
Added parameters to Tables 4 and 5. Removed System Monitor and ADC parameters.
Changed parameters in Tables 1, 2, 3, 7, and 11. Added
Characteristics
parameters to the following tables: 4–6, 14, 16–30, 32–40, and 46.
Changed the notes in
Changed description in
Table
Added RocketIO and PowerPC parameters to
conditions from V
and Output Levels
RocketIO Switching Characteristics
Revised
requirements to ensure maximum operating frequencies for the DCM. Added parameters to
Table
Revised V
Revised symbols and values in the Processor tables:
T
CLKOUT_FREQ_FX_LF_MR_MIN in
Table
Changed V
in
LVCMOS25 Standard, with DCM in Source-Synchronous
XC4VLX160-FF1513 in
tables. Revised the -10 and -11 speeds in most of the switching characteristics tables.
Updated to speed specification v1.56. Added V
information in
for DCMs to
CLKOUT_FREQ_FX_LF_MS_MIN in
Table
Corrected V
Levels
requirements ISE7.1i SP4, to description above
Table 14
Table
Table
Table
Table
DCREF
Table
45. Added parameters to
54,
47. Corrected units in
46. Added more data to the T
25, and moved RXOOB
26. Moved TXOOB
49. Added
2: Removed Note 1. Recommended maximum voltage drop for V
to
in
25. Added Note 4 to
Table
and
Table
Table
IN
Table
IL
OCM
and V
Table
and V
Table
Table
35. Along with changes to
55,
12. Revised SFI-4.1 performance values in
24. Corrected the CLKOUT_FREQ_FX_HF_MS_MIN in
in
section. Added
Production Stepping
IDIFF
43. Added global clock tree maximum frequency to
TS
IH
Table
Table
23. Edited
13. Corrected T
section. Added
for LVCMOS15 in
in
Table
and V
www.xilinx.com
Table
Table 1
Table
VDPP
8. Revised
56,
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
2. Added Set/Reset parameters to
Table
ICM
Table
Table
35. Changed Set/Reset in
VDPP
60. Added values for -12 speed specifications to most of the
Table 15
to
Table
and Note 4. Revised typical P
in
Switching Characteristics
Table
59.
Table
50. Added
58,
to
CKSKEW
PROGRAM
PowerPC Switching Characteristics
Table
46. Changed DCM_TAP_MS_MIN in
Table
Table
Table
section. Removed Table 31 from version 1.4.
Table
12. Added RSDS to
Table
and
Revisions
section.
9. Revised
Table 43
11. Added
45. Added footnotes 3 and 4 to
12. Added conditions to T
46, and the “Input Clock Period Jitter” in
in
Table
59,
7. Revised
in
Table
Table
Table
CC_CONFIG
Table
Table
Table
16. Edited
and
57:
Table
1,
59.
Table 16
RocketIO MGT Clock DC Input
43. Added DRP configuration timing
14. Added -11X speed grade to
Table
Table
60,
Table
Global Clock Setup and Hold for
Table
Interface Performance
13. Added
note to
Table
Table
Table
2, and
Table
section and
50, there are three new
37. Changed PSCLK units in
CPU
14. Replaced value for V
through
Table 32
61,
13. Added software tools
Mode. Added value for
27. Added note 4 to
Table
specification in
24. Added note 2 to
Table
Table
RocketIO DC Input
DJ
Table
CCAUX
Table
2. Clarified design
and
and T
Table
Table
3. Removed
62.
section. Added
Table
Table 45
44. Corrected
Table
22. Revised
is 10 mV/ms.
RJ
45, the
14. Added
50.
in
Table
33.
and
EYE
3.
52