XC4VFX20 XILINX [Xilinx, Inc], XC4VFX20 Datasheet - Page 47

• Manufacturer Part Number: XC4VFX20
• Description: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Table 58: Global Clock Setup and Hold for LVCMOS25 Standard, without DCM
DS302 (v3.2) April 10, 2008
Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
PSFD
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the
Global Clock input signal with the slowest route and heaviest load.
IFF = Input Flip-Flop or Latch.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
Symbol
/ T
PHFD
R
Full Delay
Global Clock and IFF
Description
(2)
without DCM
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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
XC4VLX100
XC4VLX160
XC4VLX200
XC4VFX100
XC4VFX140
XC4VSX25
XC4VSX35
XC4VSX55
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
Device
(1)
–0.09
1.82
0.11
1.79
0.20
2.06
0.13
2.39
0.04
2.36
0.16
4.85
2.56
0.46
2.12
0.14
2.10
0.21
1.99
0.57
1.82
0.12
1.75
0.38
1.82
0.64
2.42
0.25
1.99
1.11
N/A
N/A
-12
Speed Grade
–0.09
2.33
0.19
2.30
0.29
2.61
0.22
2.99
0.12
2.96
0.26
5.83
3.21
0.59
3.57
0.64
2.68
0.23
2.66
0.30
2.53
0.71
2.33
0.20
2.26
0.49
2.34
0.78
3.03
0.35
2.21
1.31
2.80
1.26
-11
–0.01
2.74
0.39
2.70
0.50
3.06
0.44
3.50
0.34
3.47
0.49
6.76
3.76
0.88
4.17
0.95
3.14
0.44
3.12
0.52
2.97
0.98
2.73
0.39
2.65
0.73
2.75
1.05
3.54
0.59
2.60
1.64
3.28
1.61
-10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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