EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 73

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–54. Global Clocking
© December 2009 Altera Corporation
Regional Clock Network
There are eight RCLK networks (RCLK[7..0]) in each quadrant of the Arria GX
device that are driven by the dedicated CLK[15..12]and CLK[7..0] input pins, by
PLL outputs, or by internal logic. The regional clock networks provide the lowest
clock delay and skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as shown in
Figure
CLK[3..0]
2–55.
Global Clock [15..0]
CLK[7..4]
CLK[15..12]
Global Clock [15..0]
Arria GX Device Handbook, Volume 1
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