EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 62
EP1AGX
Manufacturer Part Number
EP1AGX
Description
Section I. Arria GX Device Data Sheet
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP1AGX.pdf
(234 pages)
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2–56
Figure 2–48. M-RAM Block LAB Row Interface
Note to
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
Arria GX Device Handbook, Volume 1
Figure
2–48:
LABs in Row
M-RAM Boundary
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
LAB Interface
Blocks
L0
L1
L2
L3
L4
L5
Port A
(Note 1)
M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Port B
R0
R1
R2
R3
R4
R5
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
LABs in Row
M-RAM Boundary
TriMatrix Memory