EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 135

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–9. PCS Latency (Part 2 of 2) (Part 2 of 2)
© December 2009 Altera Corporation
BASIC
Single
Width
Notes to
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
(3) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set gap allowed by the
protocol, actual PPM difference between the reference clocks, and so forth.
Table
4–9:
8/10-bit channel width;
with Rate Matcher
8/10-bit channel width;
without Rate Matcher
16/20-bit channel width;
with Rate Matcher
16/20-bit channel width;
without Rate Matcher
Table 4–10
3.125 Gbps. The specification is for measurement at the package ball.
Table 4–10. Typical V
Table 4–11. Typical V
Table 4–12. Typical Pre-Emphasis (First Post-Tap),
V
400
600
800
OD
V
V
V
V
OD
V
cc
Typical (mV)
cc
OD
cc
Setting (mV)
HTX = 1.5 V
HTX = 1.2 V
Typical (mV)
HTX = 1.5 V
through
2–2.5
2–2.5
4–5
4–5
OD
OD
Table 4–13
Setting, TX Term = 100 
Setting, TX Term = 100 
24%
—
—
—
—
—
—
320
344
1
400
430
5.5–6.5
show the typical V
11–13
—
—
First Post Tap Pre-Emphasis Level
62%
31%
20%
480
500
2
600
625
0.5
0.5
Receiver PCS Latency
1
1
TX Term = 100
(Note 1)
V
V
OD
—
—
—
—
OD
Setting (mV)
112%
Setting (mV)
OD
56%
35%
640
664
3
800
830
for data rates from 600 Mbps to
1
1
1
1

Arria GX Device Handbook, Volume 1
1
1
1
1
184%
86%
53%
1000
1020
4
800
816
1–2
1–2
1–2
1–2
—
—
—
1
122%
73%
—
1200
1200
5
960
960
19–23
11–14
8–10
6–7
4–13