EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 37

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–27. LAB-Wide Control Signals
Adaptive Logic Modules
© December 2009 Altera Corporation
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Figure 2–27
The basic building block of logic in the Arria GX architecture is the ALM. The ALM
provides advanced features with efficient logic utilization. Each ALM contains a
variety of look-up table (LUT)-based resources that can be divided between two
adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can
implement various combinations of two functions. This adaptability allows the ALM
to be completely backward-compatible with four-input LUT architectures. One ALM
can also implement any function of up to six inputs and certain seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, the ALM can
efficiently implement various arithmetic functions and shift registers. Each ALM
drives all types of interconnects: local, row, column, carry chain, shared arithmetic
chain, register chain, and direct link interconnects.
block diagram of the Arria GX ALM while
the connections in the ALM.
6
6
6
shows the LAB control signal generation circuit.
labclk0
clock signals per LAB.
There are two unique
or asyncload
or labpreset
labclkena0
labclk1
labclkena1
Figure 2–29
labclk2
labclkena2
Figure 2–28
shows a detailed view of all
syncload
Arria GX Device Handbook, Volume 1
labclr0
shows a high-level
labclr1
synclr
2–31