EPF81188A ALTERA [Altera Corporation], EPF81188A Datasheet - Page 34

• Manufacturer Part Number: EPF81188A
• Description: PROGRAMMABLE LOGIC DEVICES FAMILY
• Manufacturer: ALTERA [Altera Corporation]

FLEX 8000 Programmable Logic Device Family Data Sheet
34
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Table 12. FLEX 8000 Timing Model Interconnect Paths
Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and
external parameters specified by Altera. Internal timing parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
These values are specified under
For the t
The t
timing analysis is required to determine actual worst-case performance.
External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
For more information on test conditions, see
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies to global and non-global clocking, and for LE and I/O element registers.
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out
IOE on row
IOE on column
ROW
Source
OD3
and t
f
and t
DIN_D
ZX3
parameters, V
delays are worst-case values for typical applications. Post-compilation timing simulation or
The FLEX 8000 timing model shows the delays for various paths and
functions in the circuit. See
parts: the LE; the IOE; and the interconnect, including the row and column
FastTrack Interconnect, LAB local interconnect, and carry and cascade
interconnect paths. Each parameter shown in
worst-case value in the “Timing Parameters” tables in this data sheet.
Hand-calculations that use the FLEX 8000 timing model and these timing
parameters can be used to estimate FLEX 8000 device performance.
Timing simulation or timing analysis after compilation is required to
determine the final worst-case performance.
interconnect paths shown in
For more information on timing parameters, go to
(Understanding FLEX 8000 Timing)
“FLEX 8000 3.3-V Device Recommended Operating Conditions”
CCIO
LE in same LAB
LE in same row, different LAB
LE in different row
IOE on column
IOE on row
LE in same row
Any LE
= 3.3 V or 5.0 V.
Application Note 76 (Understanding FLEX 8000 Timing)
Destination
Figure
Figure
19. This model contains three distinct
in this data book.
19.
Table 12
Figure 19
t
t
t
t
t
t
t
LOCAL
ROW
COL
COL
ROW
ROW
COL
Application Note 76
Total Delay
+ t
+ t
+ t
+ t
summarizes the
Altera Corporation
ROW
ROW
is expressed as a
LOCAL
LOCAL
in this data book.
on
+ t
+ t
page
LOCAL
LOCAL
29.