EPF81188A ALTERA [Altera Corporation], EPF81188A Datasheet - Page 33

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EPF81188A

Manufacturer Part Number
EPF81188A
Description
PROGRAMMABLE LOGIC DEVICES FAMILY
Manufacturer
ALTERA [Altera Corporation]
Datasheet

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Altera Corporation
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Symbol
ODH
Table 9. FLEX 8000 LE Timing Parameters
LUT
CLUT
RLUT
GATE
CASC
CICO
CGEN
CGENR
C
CH
CL
CO
COMB
SU
H
PRE
CLR
LABCASC
LABCARRY
LOCAL
ROW
COL
DIN_C
DIN_D
DIN_IO
Table 11. FLEX 8000 External Reference Timing Characteristics
Table 10. FLEX 8000 Interconnect Timing Parameters
DRR
Symbol
Symbol
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Cascade gate delay
Cascade chain routing delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
LE register control signal delay
LE register clock high time
LE register clock low time
LE register clock-to-output delay
Combinatorial delay
LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or load
LE register hold time after clock
LE register preset delay
LE register clear delay
Cascade delay between LEs in different LABs
Carry delay between LEs in different LABs
LAB local interconnect delay
Row interconnect routing delay,
Column interconnect routing delay
Dedicated input to LE control delay
Dedicated input to LE data delay,
Dedicated input to IOE control delay
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects,
Output data hold time after clock,
FLEX 8000 Programmable Logic Device Family Data Sheet
Note (1)
Note (4)
Note (7)
Note (4)
Parameter
Parameter
Parameter
Note (1)
Note (5)
Note (6)
33

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