EPF81188A ALTERA [Altera Corporation], EPF81188A Datasheet - Page 16
EPF81188A
Manufacturer Part Number
EPF81188A
Description
PROGRAMMABLE LOGIC DEVICES FAMILY
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EPF81188A.pdf
(61 pages)
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FLEX 8000 Programmable Logic Device Family Data Sheet
16
FastTrack Interconnect
In the FLEX 8000 architecture, connections between LEs and device I/O
pins are provided by the FastTrack Interconnect, a series of continuous
horizontal (row) and vertical (column) routing channels that traverse the
entire FLEX 8000 device. This device-wide routing structure provides
predictable performance even in complex designs. In contrast, the
segmented routing structure in FPGAs requires switch matrices to
connect a variable number of routing paths, which increases the delays
between logic resources and reduces performance.
The LABs within FLEX 8000 devices are arranged into a matrix of
columns and rows. Each row of LABs has a dedicated row interconnect
that routes signals both into and out of the LABs in the row. The row
interconnect can then drive I/O pins or feed other LABs in the device.
Figure 8
Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect
Note:
(1)
Row Channels
See
Note (1)
Table 4
shows how an LE drives the row and column interconnect.
Each LE drives one
row channel.
for the number of row channels.
LE1
LE2
to Local
Feedback
to Local
Feedback
Each LE drives up to
two column channels.
Altera Corporation
16 Column
Channels