SAA7103 PHILIPS [NXP Semiconductors], SAA7103 Datasheet - Page 49

• Manufacturer Part Number: SAA7103
• Description: Digital video encoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 64 Subaddress 6DH
Table 65 Subaddress 6EH
Table 66 Logic levels and function of PHRES
Table 67 Logic levels and function of LDEL
Table 68 Logic levels and function of FLC
2001 Sep 25
VTRIG
BLCKON
PHRES
LDEL
FLC
DATA BYTE
DATA BYTE
PHRES1
Digital video encoder
LDEL1
FLC1
0
0
1
1
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
DATA BYTE
PHRES0
LDEL0
FLC0
sets the vertical trigger phase related to chip-internal vertical input
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
0
1
encoder in normal operation mode; default after reset
output signal is forced to blanking level
selects the phase reset mode of the colour subcarrier generator; see Table 66
selects the delay on luminance path with reference to chrominance path; see Table 67
field length control; see Table 68
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
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DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAA7102; SAA7103
Product specification