SAA7103 PHILIPS [NXP Semiconductors], SAA7103 Datasheet - Page 45

• Manufacturer Part Number: SAA7103
• Description: Digital video encoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 49 Subaddress 3AH
Table 50 Subaddress 54H
Table 51 Subaddresses 55H to 59H
2001 Sep 25
CBENB
SYMP
DEMOFF
CSYNC
Y2C
UV2C
VPSEN
CCIRS
EDGE2
EDGE1
VPS5
VPS11
VPS12
VPS13
VPS14
DATA BYTE
DATA BYTE
DATA BYTE
Digital video encoder
fifth byte of video programming system data
eleventh byte of video programming system data
twelfth byte of video programming system data
thirteenth byte of video programming system data
fourteenth byte of video programming system data
LEVEL
LEVEL
LOGIC
LOGIC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
data from input ports is encoded
colour bar with fixed colours is encoded
horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default
after reset
horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at PD port
Y-C
Y-C
pin 26 provides a horizontal sync for non-interlaced VGA components output (at PIXCLK)
pin 26 provides a composite sync for interlaced components output (at XTAL clock)
input luminance data is twos complement from PD input port
input luminance data is straight binary from PD input port; default after reset
input colour difference data is twos complement from PD input port
input colour difference data is straight binary from PD input port; default after reset
video programming system data insertion is disabled; default after reset
video programming system data insertion in line 16 is enabled
If SYMP = 1, horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible
data at MP2 port; default after reset.
If SYMP = 1, horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible
data at MP1 port.
internal PPD2 data is sampled on the rising clock edge
internal PPD2 data is sampled on the falling clock edge; see Tables 25 to 29; default after
reset
internal PPD1 data is sampled on the rising clock edge; see Tables 25 to 29; default after
reset
internal PPD1 data is sampled on the falling clock edge
B
B
-C
-C
R
R
to RGB dematrix is active; default after reset
to RGB dematrix is bypassed
DESCRIPTION
45
DESCRIPTION
DESCRIPTION
in line 16; LSB first; all other bytes are not
relevant for VPS
SAA7102; SAA7103
REMARKS
Product specification