ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 8

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

ADSP-BF561
ing the appropriate values into the Interrupt Assignment
Registers (SIC_IAR7–0).
SIC and the default mappings into the CEC.
Table 2. System Interrupt Controller (SIC)
Peripheral Interrupt Event
PLL wakeup
DMA1 Error (generic)
DMA2 Error (generic)
IMDMA Error
PPI0 Error
PPI1 Error
SPORT0 Error
SPORT1 Error
SPI Error
UART Error
Reserved
DMA1 Channel 0 Interrupt (PPI0)
DMA1 Channel 1 Interrupt (PPI1)
DMA1 Channel 2 Interrupt
DMA1 Channel 3 Interrupt
DMA1 Channel 4 Interrupt
DMA1 Channel 5 Interrupt
DMA1 Channel 6 Interrupt
DMA1 Channel 7 Interrupt
DMA1 Channel 8 Interrupt
DMA1 Channel 9 Interrupt
DMA1 Channel 10 Interrupt
DMA1 Channel 11 Interrupt
DMA2 Channel 0 Interrupt (SPORT0 RX)
DMA2 Channel 1 Interrupt (SPORT0 TX)
DMA2 Channel 2 Interrupt (SPORT1 RX)
DMA2 Channel 3 Interrupt (SPORT1 TX)
DMA2 Channel 4 Interrupt (SPI)
DMA2 Channel 5 Interrupt (UART RX)
DMA2 Channel 6 Interrupt (UART TX)
DMA2 Channel 7 Interrupt
DMA2 Channel 8 Interrupt
DMA2 Channel 9 Interrupt
DMA2 Channel 10 Interrupt
DMA2 Channel 11 Interrupt
Timer0 Interrupt
Timer1 Interrupt
Timer2 Interrupt
Timer3 Interrupt
Timer4 Interrupt
Timer5 Interrupt
Timer6 Interrupt
Table 2
describes the inputs into the
Rev. A | Page 8 of 60 | May 2006
Default
Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
Table 2. System Interrupt Controller (SIC) (Continued)
Event Control
The ADSP-BF561 provides the user with a very flexible mecha-
nism to control the processing of events. In the CEC, three
registers are used to coordinate and control events. Each of the
registers is 16 bits wide, while each bit represents a particular
event class.
Peripheral Interrupt Event
Timer7 Interrupt
Timer8 Interrupt
Timer9 Interrupt
Timer10 Interrupt
Timer11 Interrupt
Programmable Flags 15–0 Interrupt A
Programmable Flags 15–0 Interrupt B
Programmable Flags 31–16 Interrupt A
Programmable Flags 31–16 Interrupt B
Programmable Flags 47–32 Interrupt A
Programmable Flags 47–32 Interrupt B
DMA1 Channel 12/13 Interrupt
(Memory DMA/Stream 0)
DMA1 Channel 14/15 Interrupt
(Memory DMA/Stream 1)
DMA2 Channel 12/13 Interrupt
(Memory DMA/Stream 0)
DMA2 Channel 14/15 Interrupt
(Memory DMA/Stream 1)
IMDMA Stream 0 Interrupt
IMDMA Stream 1 Interrupt
Watchdog Timer Interrupt
Reserved
Reserved
Supplemental Interrupt 0
Supplemental Interrupt 1
• CEC Interrupt Latch Register (ILAT) – The ILAT register
• CEC Interrupt Mask Register (IMASK) – The IMASK reg-
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
may be written only when its corresponding IMASK bit is
cleared.
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event
thereby preventing the processor from servicing the event
even though the event may be latched in the ILAT register.
This register may be read from or written to while in super-
Default
Mapping
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG8
IVG8
IVG9
IVG9
IVG12
IVG12
IVG13
IVG7
IVG7
IVG7
IVG7