ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 11

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

The baud rate, serial data format, error code generation and sta-
tus, and interrupts for the UART port are programmable.
The UART programmable features include:
The UART port’s clock rate is calculated as:
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA) serial infrared physical
layer link specification (SIR) protocol.
PROGRAMMABLE FLAGS (PFx)
The ADSP-BF561 has 48 bidirectional, general-purpose I/O,
programmable flag (PF47–0) pins. The programmable flag pins
have special functions for SPI port operation. Each programma-
ble flag can be individually controlled by manipulation of the
flag control, status, and interrupt registers as follows:
• Supporting bit rates ranging from (f
• Supporting data formats from seven bits to 12 bits per
• Both transmit and receive operations can be configured to
• Flag Direction Control Register – Specifies the direction of
• Flag Control and Status Registers – Rather than forcing the
• Flag Interrupt Mask Registers – The Flag Interrupt Mask
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
second to (f
frame.
generate maskable interrupts to the processor.
each individual PFx pin as input or output.
software to use a read-modify-write process to control the
setting of individual flags, the ADSP-BF561 employs a
“write one to set” and “write one to clear” mechanism that
allows any combination of individual flags to be set or
cleared in a single instruction, without affecting the level of
any other flags. Two control registers are provided, one
register is written-to in order to set flag values, while
another register is written-to in order to clear flag values.
Reading the flag status register allows software to interro-
gate the sense of the flags.
Registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the Flag Control Reg-
isters that are used to set and clear individual flag values,
one Flag Interrupt Mask Register sets bits to enable an
interrupt function, and the other Flag Interrupt Mask Reg-
ister clears bits to disable an interrupt function. PFx pins
UART Clock Rate
SCLK
/16) bits per second.
=
----------------------------------------------- -
16
UART_Divisor
f
SCLK
SCLK
/1,048,576) bits per
Rev. A | Page 11 of 60 | May 2006
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF561 processor provides two parallel peripheral
interfaces (PPI0, PPI1) that can connect directly to parallel A/D
and D/A converters, ITU-R 601/656 video encoders and decod-
ers, and other general-purpose peripherals. Each PPI consists of
a dedicated input clock pin, up to three frame synchronization
pins, and up to 16 data pins. The input clock supports parallel
data rates up to half the system clock rate.
In ITU-R 656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
Three distinct ITU-R 656 modes are supported:
Though not explicitly supported, ITU-R 656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Flag Interrupt Sensitivity Registers – The Flag Interrupt
• Active video only – The PPI does not read in any data
• Vertical blanking only – The PPI only transfers vertical
• Entire field – The entire incoming bitstream is read in
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
defined as inputs can be configured to generate hardware
interrupts, while output PFx pins can be configured to gen-
erate software interrupts.
Sensitivity Registers specify whether individual PFx pins
are level- or edge-sensitive and specify, if edge-sensitive,
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge sensitivity.
between the end of active video (EAV) and start of active
video (SAV) preamble symbols, or any data present during
the vertical blanking intervals. In this mode, the control
byte sequences are not stored to memory; they are filtered
by the PPI.
blanking interval (VBI) data, as well as horizontal blanking
information and control byte sequences on VBI lines.
through the PPI. This includes active video, control pream-
ble sequences, and ancillary data that may be embedded in
horizontal and vertical blanking intervals.
ADSP-BF561