ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 19

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ADSP-BF561_06

Manufacturer Part Number
ADSP-BF561_06
Description
Blackfin Embedded Symmetric Multiprocessor
Manufacturer
AD [Analog Devices]
Datasheet
Table 8. Pin Descriptions (Continued)
1
Pin Name
JTAG
Clock
Mode Controls
Voltage Regulator
Supplies
Refer to
EMU
TCK
TDO
TDI
TMS
TRST
CLKIN
XTAL
RESET
NMI0
NMI1
BMODE1–0
SLEEP
BYPASS
VROUT1–0
VDDEXT
VDDINT
GND
No Connection
Figure 27 on Page 41
to
Type Function
O
I
O
I
I
I
I
O
I
I
I
I
O
I
O
P
P
G
NC
Figure 31 on Page
Emulation Output
JTAG Clock
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset
Clock input
Crystal connection
Chip reset signal
Nonmaskable Interrupt Core A
Nonmaskable Interrupt Core B
Dedicated Mode Pin, Configures the Boot Mode
that Follows a Hardware or Software Reset
Sleep
PLL BYPASS Control
Regulation Output
Power Supply
Power Supply
Power Supply Return
NC
42.
Rev. A | Page 19 of 60 | May 2006
Driver
Type
C
C
C
1
Pull-Up/Down Requirement
None
Internal Pull-down
None
Internal Pull-down
Internal Pull-down
External Pull-down Necessary If JTAG Not Used
Pull-down Required If Function Not Used
Pull-down Required If Function Not Used
Pull-up or Pull-down Required
None
N/A
N/A
Needs to be at a Level or Clocking
None
Always Active if Core Power On
Pull-up or Pull-down Required
N/A
N/A
N/A
ADSP-BF561

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