XCR3128-10PC100C XILINX [Xilinx, Inc], XCR3128-10PC100C Datasheet - Page 5

• Manufacturer Part Number: XCR3128-10PC100C
• Description: XCR3128: 128 Macrocell CPLD
• Manufacturer: XILINX [Xilinx, Inc]

XCR3128: 128 Macrocell CPLD
Simple Timing Model
Figure 4
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
because the timing models of competing architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
Figure 4: CoolRunner Timing Model
5
shows the CoolRunner Timing Model. The Cool-
PD
, t
GLOBAL CLOCK PIN
SU
, and t
INPUT PIN
INPUT PIN
CO
. In other competing architec-
t
t
SU_PLA
SU_PAL
REGISTERED
= PAL ONLY
= PAL + PLA
t
t
PD_PLA
PD_PAL
www.xilinx.com
1-800-255-7778
= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA
D
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Frequency of our XCR3128 TotalCMOS CPLD (data taken
w/eight up/down, loadable 16 bit counters at 3.3V, 25 C).
Q
REGISTERED
Figure 5
t
CO
and
DS034 (v1.2) August 10, 2000
Table 1
OUTPUT PIN
OUTPUT PIN
SP00441
showing the I
CC
vs.
R