XCR3128-10PC100C XILINX [Xilinx, Inc], XCR3128-10PC100C Datasheet - Page 3

• Manufacturer Part Number: XCR3128-10PC100C
• Description: XCR3128: 128 Macrocell CPLD
• Manufacturer: XILINX [Xilinx, Inc]

XCR3128: 128 Macrocell CPLD
Logic Block Architecture
Figure 2
block contains control terms, a PAL array, a PLA array, and
16 macrocells. the six control terms can individually be con-
figured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 mac-
rocells’ flip-flops. The PAL array consists of a programma-
ble AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programma-
ble OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
Figure 2: Xilinx XPLA Logic Block Architecture
3
illustrates the logic block architecture. Each logic
36 ZIA INPUTS
CONTROL
ARRAY
ARRAY
PLA
PAL
(32)
5
6
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Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
through the PAL array is 10 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 2.5 ns.
So the total pin-to-pin t
product terms is 12.5 ns (10 ns for the PAL + 2.5 ns for the
PLA).
PD
for the XCR3128 using six to 37
DS034 (v1.2) August 10, 2000
PD
of the XCR3128 device
SP00435A
R