xcr3128 Xilinx Corp., xcr3128 Datasheet
xcr3128
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xcr3128 Summary of contents
Page 1
... Xilinx. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZP design technique, the XCR3128 offers true pin-to-pin speeds of 10 ns, while simultaneously delivering power that is less than 100 A at standby without the need for ‘ turbo-bits’ or other power-down schemes ...
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... R The XCR3128 CPLD is electrically reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The XCR3128 also includes an industry-standard, IEEE 1149.1, JTAG interface through which in-system program- ming (ISP) and reprogramming of the device is supported. XPLA Architecture Figure 1 shows a high level block diagram of a 128 macro- cell device implementing the XPLA architecture ...
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... The additional propagation delay incurred by a mac- rocell using one or all 32 PLA product terms is just 2.5 ns. So the total pin-to-pin t PD product terms is 12.5 ns (10 ns for the PAL + 2.5 ns for the PLA). 6 www.xilinx.com 1-800-255-7778 R of the XCR3128 device PD for the XCR3128 using six to 37 SP00435A DS034 (v1.2) August 10, 2000 ...
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... There are four clocks available on the XCR3128 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2 ...
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... Xilinx to offer CPLDs which are both high performance and low power, breaking the para- digm that to have low power, you must have low perfor- mance. Refer to Frequency of our XCR3128 TotalCMOS CPLD (data taken w/eight up/down, loadable 16 bit counters at 3.3V COMBINATORIAL PAL ONLY ...
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... Reduces/eliminates the need for expensive test equipment - Reduces test preparation time - Reduces spare board inventories The Xilinx XCR3128's JTAG interface includes a TAP Port and a TAP Controller, both of which are defined by the IEEE 1149.1 JTAG Specification. As implemented in the Xilinx www.xilinx.com 1-800-255-7778 XCR3128: 128 Macrocell CPLD ...
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... TDI, and TDO. The fifth signal defined by the JTAG specifi- cation is TRST* (Test Reset). TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Xilinx XCR3128 saves an I/O pin for gen- eral purpose use by not implementing the optional TRST* signal in the JTAG interface. Instead, the Xilinx XCR3128 supports the test reset functionality through the use of its power up reset circuit, which is included in all Xilinx CPLDs ...
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... A set of low-level ISP basic commands implemented in the XCR3128 enable this feature. The ISP commands implemented in the Xilinx XCR3128 are specified in Please note that an ENABLE command must precede all ...
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... Third party programmers • High-End JTAG and ISP tools A Boundary-Scan Description Language (BSDL) descrip- tion of the XCR3128 is also available from Xilinx for use in test program development. For more details on JTAG and ISP for the XCR3128, refer to the related application note: JTAG and ISP Overview for Xilinx XPLA1 and XPLA2 CPLDs ...
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... One pin at a time for no longer than 1 second MHz AMB 1MHz AMB 1MHz AMB or ground. This parameter guaranteed by design and characterization, not testing. CC www.xilinx.com 1-800-255-7778 XCR3128: 128 Macrocell CPLD Min. Max. Unit -0.5 7 ...
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... XCR3128: 128 Macrocell CPLD AC Electrical Characteristics Commercial +70 C; 3.0V AMB Symbol Parameter t Propagation delay time, input (or feedback node) to PD_PAL output through PAL t Propagation delay time, input (or feedback node) to PD_PLA output through PAL + PLA t Clock to out (global synchronous clock from pin Setup time (from input or feedback node) through PAL ...
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... One pin at a time for no longer than 1 second MHz AMB 1MHz AMB 1MHz AMB or ground. This parameter guaranteed by design and characterization, not testing. CC www.xilinx.com 1-800-255-7778 XCR3128: 128 Macrocell CPLD Min. Max. Unit 0.8 V 2.0 V -1.2 V 0.5 V 2.4 V -10 ...
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... XCR3128: 128 Macrocell CPLD AC Electrical Characteristics Industrial: - +85 C; 3.0V AMB Symbol t Propagation delay time, input (or feedback node) to output through PAL PD_PAL t Propagation delay time, input (or feedback node) to output through PD_PLA PAL + PLA t Clock to out (global synchronous clock from pin Setup time (from input or feedback node) through PAL ...
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... Figure 7: Voltage Waveform Table 3 25°C) CC SP00466A Number Of Outputs Typical (ns) www.xilinx.com 1-800-255-7778 XCR3128: 128 Macrocell CPLD VALUES 390 390 Open Closed Closed Closed Closed Closed pF, and 3-state levels are PLZ ...
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... XCR3128: 128 Macrocell CPLD Pin Function And Layout XCR3128: 100-pin and 160-pin PQFP Pin Function Table Function PQFP Pin # Pin # 100-pin 160-pin 1 I/O- I/O- I/O- I/O- I/O-B15 (TDI I/O-B13 I/O-B12 I/O-B10 I/O-B15 (TDI) ...
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... R XCR3128: 84-pin PLCC, 100-Pin VQFP, and 128-pin TQFP Pin Function Table Function Pin Pin # # PLCC VQFP TQFP 1 IN1 I/O-A2 I/O- IN3 I/O-A0 I/O- I/O- I/O-A15/ I/O-B15 NC 36 CLK3 (TDI) 5 I/O-A13 I/O-B13 I/O-A12 I/O-B12 GND I/O-B10 I/O-A10 I/O-B8 I/O-B15 ...
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... XCR3128: 128 Macrocell CPLD 84-pin PLCC PLCC 100-pin PQFP 100 81 1 PQFP QFP 100-pin VQFP 100 76 1 VQFP TQFP 128-pin TQFP 74 54 SP00467A 160-pin PQFP 80 51 SP00468A 75 51 SP00485A www.xilinx.com 1-800-255-7778 128 103 1 102 TQFP ...
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... R Ordering Information Example: XCR3128 - Device Type Speed Options Speed Options -15 pin-to-pin delay -12 pin-to-pin delay -10 pin-to-pin delay Component Availability Pins 84 Type Plastic PLCC Code PC84 XCR3128 - - -10 C Revision Table Date Version # 8/4/99 1 ...