DAC1201D125HL NXP [NXP Semiconductors], DAC1201D125HL Datasheet - Page 17

• Manufacturer Part Number: DAC1201D125HL
• Description: Dual 12-bit DAC, up to 125 Msps
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1201D125_1
Product data sheet
10.3 Timing
10.4 DAC transfer function
The DAC1201D125 can operate at an update rate up to 125 Msps. This generates an
input data rate of 125 MHz in Dual-port mode and 250 MHz in Interleaved mode. The
timing of the DAC1201D125 is shown in
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
A typical set-up time of 0 ns and a hold time of 0.6 ns enables the DAC1201D125 to be
easily integrated into any application.
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
The output current depends on the digital input data:
I
I
O fs
IOUTP
Fig 18. Timing of the DAC1201D125
•
•
A configuration resulting in the same timing for the signals WRTA/WRTB and
CLKA/CLKB, can be achieved either by synchronizing them or by connecting them
together.
The rising edge of the CLKA/CLKB signal can also be placed in a range from half a
period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns
after the rising edge of the WRTA/WRTB signal.
=
=
I
IOUTP
I
O fs
+
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
I
IOUTN
DATA
--------------- -
DA11 to DA0/
DB11 to DB0
4096
Rev. 01 — 27 November 2008
WRTA/
WRTB
CLKA/
CLKB
t
w(WRT)
I
IOUTN
t
w(CLK)
Figure
=
I
t
O fs
su(i)
18.
--------------------------------------
10 %
4095 DATA
Dual 12-bit DAC, up to 125 Msps
t
h(i)
t
d(clk)
4096
DAC1201D125
–
t
t
s
t
t
d
90 %
001aaj117
© NXP B.V. 2008. All rights reserved.
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