DAC1201D125HL NXP [NXP Semiconductors], DAC1201D125HL Datasheet

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DAC1201D125HL

Manufacturer Part Number
DAC1201D125HL
Description
Dual 12-bit DAC, up to 125 Msps
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.DAC1201D125HL.pdf (26 pages)

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Quantity:
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Part Number:
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1. General description
2. Features
3. Applications
The DAC1201D125 is a dual-port, high-speed, 2-channel CMOS Digital-to-Analog
Converter (DAC), optimized for high dynamic performance with low power dissipation.
Supporting an update rate of up to 125 Msps, the DAC1201D125 is suitable for Direct IF
applications.
Separate write inputs allow data to be written to the two DAC ports independently of one
another. Two separate clocks control the update rate of each DAC port.
The DAC1201D125 can interface two separate data ports or one single interleaved
high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its
original I and Q data and latched. The I and Q data is then converted by the two DACs and
updated at half the input data rate.
Each DAC port has a high-impedance differential current output, suitable for both
single-ended and differential analog output configurations.
The DAC1201D125 is pin compatible with the AD9765, DAC2902 and DAC5662.
I
I
I
I
I
I
I
I
I
I
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Rev. 01 — 27 November 2008
Dual 12-bit resolution
125 Msps update rate
Single 3.3 V supply
Dual-port or Interleaved data modes
1.8 V, 3.3 V and 5 V compatible digital
inputs
Internal and external reference
2 mA to 20 mA full-scale output current
Quadrature modulation
Medical/test instrumentation
Direct IF applications
I
I
I
I
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I
Typical 185 mW power dissipation
16 mW power-down
SFDR: 81 dBc; f
SFDR: 78 dBc; f
f
SFDR: 74 dBc; f
f
LQFP48 package
Industrial temperature range of
Direct digital frequency synthesis
Arbitrary waveform generator
s
s
40 C to +85 C
= 52 Msps; 12 dBFS
= 78 Msps
o
o
o
= 1 MHz; f
= 1 MHz;
= 10.4 MHz;
Product data sheet
s
= 52 Msps

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DAC1201D125HL Summary of contents

Page 1

DAC1201D125 Dual 12-bit DAC 125 Msps Rev. 01 — 27 November 2008 1. General description The DAC1201D125 is a dual-port, high-speed, 2-channel CMOS Digital-to-Analog Converter (DAC), optimized for high dynamic performance with low power dissipation. Supporting an update ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name DAC1201D125HL LQFP48 5. Block diagram Fig 1. DAC1201D125_1 Product data sheet Description plastic low profile quad flat package; 48 leads; body 7 12 INPUT A 12 DA11 to DA0 LATCH WRTA/IQWRT CLKA/IQCLK DAC1201D125 CLKB/IQRESET WRTB/IQSEL ...

Page 3

... DA5 DA4 DA3 DA2 DA1 DA0 n.c. DAC1201D125_1 Product data sheet DA11 1 DA10 2 3 DA9 DA8 4 DA7 5 6 DA6 DAC1201D125HL 7 DA5 DA4 8 DA3 9 10 DA2 DA1 11 DA0 12 Pin configuration SOT313-2 (LQFP48) Pin description [1] Pin Type Description 1 I DAC A, data input bit 11 (MSB) ...

Page 4

NXP Semiconductors Table 2. Symbol n.c. DGND V DDD WRTA/IQWRT CLKA/IQCLK CLKB/IQRESET WRTB/IQSEL DGND V DDD DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 n.c. n.c. PWD AGND IOUTBP IOUTBN BVIRES GAINCTRL REFIO AVIRES IOUTAN IOUTAP ...

Page 5

NXP Semiconductors 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V digital supply voltage DDD V analog supply voltage DDA V supply voltage difference DD V input voltage I ...

Page 6

NXP Semiconductors Table 5. Characteristics …continued 3.3 V; AGND and DGND connected together; I DDD DDA measured amb Symbol Parameter Digital inputs V LOW-level input voltage IL V HIGH-level input voltage ...

Page 7

NXP Semiconductors Table 5. Characteristics …continued 3.3 V; AGND and DGND connected together; I DDD DDA measured amb Symbol Parameter Dynamic performance SFDR spurious free dynamic range THD total harmonic distortion ...

Page 8

NXP Semiconductors SFDR (dBc) (1) f (2) f (3) f (4) f Fig 3. DAC1201D125_1 Product data sheet 80 (1) 76 (2) 72 ( MHz MHz ...

Page 9

NXP Semiconductors (dBm (dBm Fig 4. DAC1201D125_1 Product data sheet 100 Msps 5.24 MHz dBFS 100 ...

Page 10

NXP Semiconductors (dBm) Fig 5. (dBm) Fig 6. DAC1201D125_1 Product data sheet 100 Msps 9.44 MHz 10.44 MHz 2-tone SFDR ...

Page 11

NXP Semiconductors (dBm) Fig 7. INL (dB) Fig 8. DAC1201D125_1 Product data sheet 100 Msps; from f = 9.5 MHz, 110 kHz spacing 8-tone SFDR 0.8 0.4 0 ...

Page 12

NXP Semiconductors DNL (dB) Fig 9. SFDR (dBc) (1) f (2) f (3) f Fig 10. SFDR full-scale at 78 Msps as a function of the output frequency DAC1201D125_1 Product data sheet 0.2 0.1 0 0.1 0.2 0 756 1512 ...

Page 13

NXP Semiconductors SFDR (dBc) (1) f (2) f (3) f Fig 11. SFDR full-scale at 125 Msps as a function of the output frequency I DDD (mA) (1) f (2) f (3) f (4) f Fig 12. Digital supply current ...

Page 14

NXP Semiconductors I DDA (mA) Fig 13. Analog supply current as a function of the output current 10. Application information 10.1 General description The DAC1201D125 is a dual 12-bit DAC operating up to 125 Msps. Each DAC consists of a ...

Page 15

NXP Semiconductors Table 6. Mode Function LOW Interleaved mode HIGH Dual-port mode 10.2.1 Dual-port mode The data and clock circuit for Dual-port mode operation is shown in Fig 14. Dual-port mode operation Each DAC has its own independent data and ...

Page 16

NXP Semiconductors 10.2.2 Interleaved mode The data and clock circuit for Interleaved mode operation is illustrated in Fig 16. Interleaved mode In Interleaved mode, both DACs use the same data and clock inputs at twice the update rate. Data enters ...

Page 17

NXP Semiconductors 10.3 Timing The DAC1201D125 can operate at an update rate up to 125 Msps. This generates an input data rate of 125 MHz in Dual-port mode and 250 MHz in Interleaved mode. The timing of the DAC1201D125 is ...

Page 18

NXP Semiconductors Table 7 Table 7. Data 0 ... 2047 ... 4095 10.5 Full-scale current adjustment The DAC1201D125 integrates one 1.25 V reference and two current sources to adjust the full-scale current in both DACs. The internal reference configuration is ...

Page 19

NXP Semiconductors An external reference can also be used for applications requiring higher accuracy or precise current adjustment. Due to the high input impedance of pin REFIO, applying an external source disables the band gap. 10.6 Gain control Table 8 ...

Page 20

NXP Semiconductors 10.7.1 Differential output using transformer The use of a differential-coupled transformer output (see distortion performance, and it helps to match the impedance and provides electrical isolation. Fig 21. Differential output with transformer The center tap is grounded to ...

Page 21

NXP Semiconductors 10.9 Alternative devices The following alternative devices are also available. Table 10. Pin compatible Type number DAC1001D125 DAC1401D125 DAC1201D125_1 Product data sheet Alternative devices Description dual 10-bit DAC dual 14-bit DAC Rev. 01 — 27 November 2008 DAC1201D125 ...

Page 22

NXP Semiconductors 10.10 Application diagram Fig 23. Application diagram DAC1201D125_1 Product data sheet R L AGND AGND 1.5 k 100 100 nF 3 DA11 1 DA10 2 DA9 3 DA8 4 DA7 5 DA6 ...

Page 23

NXP Semiconductors 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original ...

Page 24

NXP Semiconductors 12. Abbreviations Table 11. Acronym DNL dBFS IF INL LSB MSB PMOS SFDR 13. Revision history Table 12. Revision history Document ID Release date DAC1201D125_1 20081127 DAC1201D125_1 Product data sheet Abbreviations Description Differential Non-Linearity deciBel Full-Scale Intermediate Frequency ...

Page 25

NXP Semiconductors 14. Legal information 14.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 26

NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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