AD5315BRM-REEL AD [Analog Devices], AD5315BRM-REEL Datasheet - Page 4

• Manufacturer Part Number: AD5315BRM-REEL
• Description: 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
• Manufacturer: AD [Analog Devices]

AD5305/AD5315/AD5325
TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
NOTES
1
2
3
4
Specifications subject to change without notice.
SCL
1
2
3
4
5
6
7
8
9
10
11
See Figure 1.
Guaranteed by design and characterization; not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
SCL’s falling edge.
C
3
B
B
is the total capacitance of one bus line in pF. t
SDA
SCL
Limit at T
(A, B Version)
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1C
400
t
9
CONDITION
START
t
4
B
MIN
4
, T
t
3
MAX
Figure 1. 2-Wire Serial Interface Timing Diagram
1, 2
R
and t
t
10
F
(V
t
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
6
measured between 0.3 V
DD
= 2.5 V to 5.5 V; all specifications T
t
2
Conditions/Comments
SCL Clock Frequency
SCL Cycle Time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive Load for Each Bus Line
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
, Fall Time of SDA when Transmitting
, Fall Time of SDA when Receiving (CMOS Compatible)
, Fall Time of SCL and SDA when Receiving
, Fall Time of SCL and SDA when Transmitting
, Rise Time of SCL and SDA when Receiving
, Rise Time of SCL and SDA when Receiving (CMOS Compatible)
–4–
t
11
, Bus Free Time between a STOP and a START Condition
, SCL Low Time
DD
, SCL High Time
, Setup Time for Repeated Start
t
, Stop Condition Setup Time
, Data Setup Time
, Start/Repeated Start Condition Hold Time
5
, Data Hold Time
, Data Hold Time
and 0.7 V
IH
min of the SCL signal) in order to bridge the undefined region of
DD
.
MIN
CONDITION
REPEATED
START
to T
t
7
MAX
t
, unless otherwise noted.)
4
t
1
CONDITION
STOP
t
8
REV. F