AD5315BRM-REEL AD [Analog Devices], AD5315BRM-REEL Datasheet

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AD5315BRM-REEL

Manufacturer Part Number
AD5315BRM-REEL
Description
2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
Manufacturer
AD [Analog Devices]
Datasheet
1.AD5315BRM-REEL.pdf (20 pages)
*Protected by U.S.Patent No. 5,969,657and 5,684,481.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FEATURES
AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP
AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP
AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
2-Wire (I
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Three Power-Down Modes
Double-Buffered Input Logic
Output Range: 0 V to V
Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
A Version:
A Version:
A Version:
2
C
®
Compatible) Serial Interface
1 LSB INL, B Version:
4 LSB INL, B Version:
16 LSB INL, B Version:
SDA
SCL
REF
A0
INTERFACE
LOGIC
POWER-ON
RESET
LDAC
0.625 LSB INL
2.5 LSB INL
10 LSB INL
FUNCTIONAL BLOCK DIAGRAM
Quad Voltage Output, 8-/10-/12-Bit DACs
2.5 V to 5.5 V, 500 A, 2-Wire Interface
REGISTER
REGISTER
REGISTER
REGISTER
INPUT
INPUT
INPUT
INPUT
AD5305/AD5315/AD5325
V
DD
GND
REGISTER
REGISTER
REGISTER
REGISTER
DAC
DAC
DAC
DAC
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus compatible at V
placed on the same bus.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit, which ensures that the DAC outputs power
up to 0 V and remain there until a valid write takes place to the
device. There is also a software clear function that resets all input
and DAC registers to 0 V. The parts contain a power-down
feature that reduces the current consumption of the devices to
200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 µW in power-down mode.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
REF IN
STRING
STRING
STRING
STRING
DAC B
DAC A
DAC C
DAC D
AD5305/AD5315/AD5325
BUFFER
BUFFER
BUFFER
BUFFER
POWER-DOWN
LOGIC
© 2004 Analog Devices, Inc. All rights reserved.
DD
< 3.6 V. Multiple devices can be
V
V
V
V
OUT
OUT
OUT
OUT
A
B
C
D
www.analog.com
*

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AD5315BRM-REEL Summary of contents

Page 1

FEATURES AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP A Version: 1 LSB INL, B Version: AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP A Version: 4 LSB INL, B Version: AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP A ...

Page 2

AD5305/AD5315/AD5325–SPECIFICATIONS C = 200 pF to GND; all specifications T L MIN A Version 1 Parameter Min PERFORMANCE AD5305 Resolution Relative Accuracy Differential Nonlinearity AD5315 Resolution Relative Accuracy Differential Nonlinearity AD5325 Resolution Relative Accuracy Differential Nonlinearity Offset ...

Page 3

A Version 1 Parameter Min POWER REQUIREMENTS V 2 (Normal Mode (Power-Down Mode 4 ...

Page 4

AD5305/AD5315/AD5325 TIMING CHARACTERISTICS Limit MIN MAX Parameter (A, B Version) f 400 SCL 100 0 0.6 7 ...

Page 5

... AD5305BRM-REEL –40°C to +105°C AD5305BRM-REEL7 –40°C to +105°C AD5315BRM –40°C to +105°C AD5315BRM-REEL –40°C to +105°C AD5315BRM-REEL7 –40°C to +105°C AD5325BRM –40°C to +105°C AD5325BRM-REEL –40°C to +105°C AD5325BRM-REEL7 –40°C to +105°C CAUTION ESD (electrostatic discharge) sensitive device ...

Page 6

AD5305/AD5315/AD5325 Pin No. Mnemonic Function 1 V Power Supply Input. These parts can be operated from 2 5.5 V and the supply should be DD decoupled to GND Buffered Analog Output Voltage from DAC A. ...

Page 7

Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state normally specified as the area of the glitch in nV-s ...

Page 8

AD5305/AD5315/AD5325–Typical Performance Characteristics 1 0.5 0 –0.5 –1.0 50 100 150 200 250 0 CODE TPC 1. AD5305 Typical INL Plot 0 0.2 ...

Page 9

0 REF 0 GAIN ERROR –0.1 –0.2 –0.3 –0.4 OFFSET ERROR –0.5 –0 (V) DD TPC 10. Offset Error and Gain Error vs. ...

Page 10

AD5305/AD5315/AD5325 300 350 400 450 500 550 600 TPC 19. I Histogram with and 0. ...

Page 11

Resistor String The resistor string section is shown in Figure simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is ...

Page 12

AD5305/AD5315/AD5325 Pointer Byte Bits The following is an explanation of the individual bits that make up the pointer byte. X Don’t care bits. 0 Reserved bits, must be set to 0. DACD 1: The following data bytes are for DAC ...

Page 13

WRITE OPERATION When writing to the AD5305/AD5315/AD5325 DACs, the user must begin with an address byte (R/W = 0), after which the DAC will acknowledge that it is prepared to receive data by pulling SCL ...

Page 14

AD5305/AD5315/AD5325 READ OPERATION When reading data back from the AD5305/AD5315/AD5325 DACs, the user begins with an address byte (R/W = 0), after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. This address ...

Page 15

DOUBLE-BUFFERED INTERFACE The AD5305/AD5315/AD5325 DACs have double-buffered interfaces consisting of two banks of registers—input registers and DAC registers. The input register is directly connected to the input shift register and the digital code is transferred to the relevant input register ...

Page 16

AD5305/AD5315/AD5325 If an output range required, the simplest solution connect the reference input this supply may not be DD very accurate and may be noisy, the AD5305/AD5315/AD5325 ...

Page 17

51.2k 0 EXT V REFIN V A OUT OUT REF 1 F 1/2 GND AD5305/ AD5315/ AD5325 * AD780/REF192 WITH OUT GND * ...

Page 18

AD5305/AD5315/AD5325 No. of Part No. Resolution DACs SINGLES AD5300 8 1 AD5310 10 1 AD5320 12 1 AD5301 8 1 AD5311 10 1 AD5321 12 1 DUALS AD5302 8 2 AD5312 10 2 AD5322 12 2 AD5303 8 2 AD5313 ...

Page 19

REV. F OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.15 0.27 SEATING 0.23 0.00 PLANE ...

Page 20

AD5305/AD5315/AD5325 Revision History Location 10/04—Data Sheet changed from REV REV. F. Changes to Figure ...

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