AD5315BRM-REEL AD [Analog Devices], AD5315BRM-REEL Datasheet - Page 11

• Manufacturer Part Number: AD5315BRM-REEL
• Description: 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
• Manufacturer: AD [Analog Devices]

Resistor String
The resistor string section is shown in Figure 5. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
DAC Reference Inputs
There is a single reference input pin for the four DACs. The
reference input is unbuffered. The user can have a reference
voltage as low as 0.25 V and as high as V
restriction due to headroom and footroom of any reference
amplifier.
It is recommended to use a buffered reference in the external
circuit (e.g., REF192). The input impedance is typically 45 kΩ.
Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to
V
2 kΩ to GND or V
The source and sink capabilities of the output amplifier can be
seen in the plot in TPC 11.
The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB
(at eight bits) of 6 µs.
POWER-ON RESET
The AD5305/AD5315/AD5325 are provided with a power-on
reset function, so that they power up in a defined state. The
power-on state is
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
REV. F
DD
• Normal operation
• Output voltage set to 0 V
when the reference is V
R
R
R
R
R
Figure 5. Resistor String
DD
, in parallel with 500 pF to GND or V
DD
. It is capable of driving a load of
TO OUTPUT
AMPLIFIER
DD
since there is no
DD
.
–11–
SERIAL INTERFACE
The AD5305/AD5315/AD5325 are controlled via an I
compatible serial bus. The DACs are connected to this bus as
slave devices (i.e., no clock is generated by the AD5305/AD5315/
AD5325 DACs). This interface is SMBus compatible at V
< 3.6 V.
The AD5305/AD5315/AD5325 have a 7-bit slave address. The
6 MSB are 000110 and the LSB is determined by the state of
the A0 pin. The facility to make hardwired changes to A0 allows
the user to use up to two of these devices on one bus.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
2. Data is transmitted over the serial bus in sequences of nine
3. When all data bits have been read or written, a STOP condi-
Read/Write Sequence
In the case of the AD5305/AD5315/AD5325, all write access
sequences and most read sequences begin with the device address
(with R/W = 0) followed by the pointer byte. This pointer byte
specifies the data format and determines which DAC is being
accessed in the subsequent read/write operation. (See Figure 6.)
In a write operation, the data follows immediately. In a read
operation, the address is resent with R/W = 1 and then the data
is read back. However, it is also possible to perform a read
operation by sending only the address with R/W = 1. The
previously loaded pointer settings are then used for the read-
back operation. See Figure 7 for a graphical explanation of the
interface.
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is the
address byte, which consists of the 7-bit slave address fol-
lowed by an R/W bit (this bit determines whether data will
be read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling SDA low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage, all
other devices on the bus remain idle while the selected device
waits for data to be written to or read from its shift register.
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
tion is established. In write mode, the master will pull the
SDA line high during the 10th clock pulse to establish a
STOP condition. In read mode, the master will issue a No
Acknowledge for the ninth clock pulse (i.e., the SDA line
remains high). The master will then bring the SDA line low
before the 10th clock pulse and then high during the 10th
clock pulse to establish a STOP condition.
MSB
X
X
Figure 6. Pointer Byte
AD5305/AD5315/AD5325
0
0
DACD
DACC DACB DACA
LSB
2
C
DD