ADV7181 AD [Analog Devices], ADV7181 Datasheet - Page 69

• Manufacturer Part Number: ADV7181
• Description: Multiformat SDTV Video Decoder
• Manufacturer: AD [Analog Devices]

Subaddress
0x49
0x4A
Register
Raw
Status 3
Read Only
Register
Register
Access
Page 2
Interrupt
Status 3
Read Only
Register
Register
Access
Page 2
Bit Description
SD_OP_50Hz
SD 60/50Hz frame rate at
output
SD_V_LOCK
SD_H_LOCK
Reserved
SCM_LOCK
SECAM Lock
Reserved
Reserved
Reserved
SD_OP_CHNG_Q
SD 60/50 Hz frame rate at
input
SD_V_LOCK_CHNG_Q
SD_H_LOCK_CHNG_Q
SD_AD_CHNG_Q
SD autodetect changed
SCM_LOCK_CHNG_Q
SECAM Lock
PAL_SW_LK_CHNG_Q
Reserved
Reserved
7
x
x
Rev. 0 | Page 69 of 96
6
x
x
5
x
x
4
0
1
0
1
Bit
3
x
x
2
0
1
0
1
1
0
1
0
1
0
0
1
0
1
Comments
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not
established
SD vertical sync lock
established
SD horizontal sync lock not
established
SD horizontal sync lock
established
Not used
SECAM Lock not established
SECAM Lock established
Not used
Not used
Not used
No Change in SD signal
standard detected at the input
A Change in SD signal standard
is detected at the input
No Change in SD vertical sync
lock status
SD vertical sync lock status has
changed.
No change in SD horizontal sync
lock status.
SD horizontal sync lock status
has changed
No change in AD_RESULT[2:0]
bits in Status Register 1.
AD_RESULT[2:0] bits in Status
Register 1 have changed
No Change in SECAM Lock
status
SECAM lock status has changed
No change in PAL swinging
burst lock status
PAL swinging burst lock status
has changed
Not used
Not used
ADV7181B
Notes
These bits
cannot be
cleared or
masked.
Register
0x4A is used
for this
purpose.
These bits
can be
cleared and
masked by
registers
0x4B and
0x4C,
respectively.