ADV7181 AD [Analog Devices], ADV7181 Datasheet - Page 64

• Manufacturer Part Number: ADV7181
• Description: Multiformat SDTV Video Decoder
• Manufacturer: AD [Analog Devices]

ADV7181B
Register
Name
Luma Gain
Control 1
Luma Gain
Control 2
VSync Field
Control 1
VSync Field
Control 2
VSync Field
Control 3
HSync
Position
Control 1
HSync
Position
Control 2
HSync
Position
Control 3
Polarity
NTSC Comb
Control
PAL Comb
Control
ADC Control
Reserved
Manual
Window
Control
Reserved
Resample
Control
Reserved
Gemstar Ctrl 1
Gemstar Ctrl 2
Gemstar Ctrl 3
Gemstar Ctrl 4
Gemstar Ctrl 5
CTI DNR Ctrl 1
CTI DNR Ctrl 2
Reserved
CTI DNR Ctrl 4
Lock Count
Reserved
Free Run Line
Length 1
Reserved
VBI Info
WSS 1
WSS 2
EDTV 1
EDTV 2
EDTV 3
CGMS 1
CGMS 2
CGMS 3
CCAP 1
CCAP 2
Letterbox 1
Letterbox 2
Letterbox 3
Reserved
CRC Enable
Reserved
ADC Switch 1
CTI_C_TH.7
DNR_TH.7
CCAP1.7
Bit 7
LAGT.1
LMG.7
VSBHO
VSEHO
HSB.7
HSE.7
PHS
CTAPSN.1
CTAPSP.1
GDECEL.15
GDECEL.7
GDECOL.15
GDECOL.7
FSCLE
WSS1.7
WSS2.7
EDTV1.7
EDTV2.7
EDTV3.7
CGMS1.7
CGMS2.7
CGMS3.7
CCAP2.7
LB_LCT.7
LB_LCM.7
LB_LCB.7
ADC1_SW.3
Bit 6
LGAT.0
LMG.6
VSBHE
VSEHE
HSB.10
HSB.6
HSE.6
CTAPSN.0
CTAPSP.0
CKILLTHR.2
SFL_INV
GDECEL.14
GDECEL.6
GDECOL.14
GDECOL.6
CTI_C_TH.6
DNR_TH.6
SRLS
LLC_PAD_SEL.2
WSS1.6
WSS2.6
EDTV1.6
EDTV2.6
EDTV3.6
CGMS1.6
CGMS2.6
CGMS3.6
CCAP1.6
CCAP2.6
LB_LCT.6
LB_LCM.6
LB_LCB.6
ADC1_SW.2
Bit 5
LMG.5
HSB.9
HSB.5
HSE.5
PVS
CCMN.2
CCMP.2
CKILLTHR.1
GDECEL.13
GDECEL.5
GDECOL.13
GDECOL.5
DNR_EN
CTI_C_TH.5
DNR_TH.5
COL.2
LLC_PAD_SEL.1
WSS1.5
WSS2.5
EDTV1.5
EDTV2.5
EDTV3.5
CGMS1.5
CGMS2.5
CGMS3.5
CCAP1.5
CCAP2.5
LB_LCT.5
LB_LCM.5
LB_LCB.5
ADC1_SW.1
Rev. 0 | Page 64 of 96
Bit 4
LMG.4
NEWAVMODE
HSB.8
HSB.4
HSE.4
CCMN.1
CCMP.1
CKILLTHR.0
GDECEL.12
GDECEL.4
GDECOL.12
GDECOL.4
CTI_C_TH.4
DNR_TH.4
COL.1
LLC_PAD_SEL.0
WSS1.4
WSS2.4
EDTV1.4
EDTV2.4
EDTV3.4
CGMS1.4
CGMS2.4
CGMS3.4
CCAP1.4
CCAP2.4
LB_LCT.4
LB_LCM.4
LB_LCB.4
ADC1_SW.0
Bit 3
LMG.11
LMG.3
HVSTIM
HSB.3
HSE.3
PF
CCMN.0
CCMP.0
PWRDN_AD C_0
GDECEL.11
GDECEL.3
GDECOL.11
GDECOL.3
CTI_AB.1
CTI_C_TH.3
DNR_TH.3
COL.0
WSS1.3
WSS2.3
EDTV1.3
EDTV2.3
EDTV3.3
CGMS1.3
CGMS2.3
CGMS3.3
CCAP1.3
CCAP2.3
LB_LCT.3
LB_LCM.3
LB_LCB.3
ADC0_SW.3
CGMSD
Bit 2
YCMN.2
YCMP.2
PWRDN_AD C_1
CTI_AB.0
ADC0_SW.2
LMG.10
LMG.2
HSE.10
HSB.2
HSE.2
GDECEL.10
GDECEL.2
GDECOL.10
GDECOL.2
CTI_C_TH.2
DNR_TH.2
CIL.2
EDTVD
WSS1.2
WSS2.2
EDTV1.2
EDTV2.2
EDTV3.2
CGMS1.2
CGMS2.2
CGMS3.2
CCAP1.2
CCAP2.2
LB_LCT.2
LB_LCM.2
LB_LCB.2
CRC_ENABLE
Bit 1
LMG.9
LMG.1
HSE.9
HSB.1
HSE.1
YCMN.1
YCMP.1
PWRDN_ADC_2
GDECEL.9
GDECEL.1
GDECOL.9
GDECOL.1
CTI_AB_EN
CTI_C_TH.1
DNR_TH.1
CIL.1
CCAPD
WSS1.1
WSS2.1
EDTV1.1
EDTV2.1
EDTV3.1
CGMS1.1
CGMS2.1
CGMS3.1
CCAP1.1
CCAP2.1
LB_LCT.1
LB_LCM.1
LB_LCB.1
ADC0_SW.1
Bit 0
LMG.8
LMG.0
HSE.8
HSB.0
HSE.0
PCLK
YCMN.0
YCMP.0
GDECEL.8
GDECEL.0
GDECOL.8
GDECOL.0
GDECAD
CTI_EN
CTI_C_TH.0
DNR_TH.0
CIL.0
WSSD
WSS1.0
WSS2.0
EDTV1.0
EDTV2.0
EDTV3.0
CGMS1.0
CGMS2.0
CGMS3.0
CCAP1.0
CCAP2.0
LB_LCT.0
LB_LCM.0
LB_LCB.0
ADC0_SW.0