ADV7181 AD [Analog Devices], ADV7181 Datasheet - Page 10

• Manufacturer Part Number: ADV7181
• Description: Multiformat SDTV Video Decoder
• Manufacturer: AD [Analog Devices]

ADV7181B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
3, 10, 24, 34, 57
32, 37, 43, 45
4, 11
23, 58
40
31
35, 36, 46–49
12, 13, 27, 28, 33,
50, 55, 56
26, 25, 19, 18, 17,
16, 15, 14, 8, 7, 6, 5,
62, 61, 60, 59
2
64
63
1
53
54
52
51
20
22
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
AIN1–AIN6
NC
P0–P15
HS
VS
FIELD
INTRQ
SDA
SCLK
ALSB
RESET
LLC
XTAL
DVDDIO
DVDDIO
NC = NO CONNECT
INTRQ
DGND
DGND
SFL
P11
P10
HS
NC
NC
P9
P8
P7
P6
P5
I
Type
G
G
P
P
P
P
O
O
O
O
O
I/O
I
I
I
O
I
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
64
17
PIN 1
INDICATOR
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in Table 82.
I
I
This pin selects the I
a write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7181B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7181B. Nominally
27 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
2
2
63
18
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).
Figure 4. 64-Lead LFCSP/LQFP Pin Configuration
62
19
61
20
60
21
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59
22
ADV7181B
(Not to Scale)
58
23
TOP VIEW
57
24
2
C address for the ADV7181B. ALSB set to a Logic 0 sets the address for
56
25
55
26
54
27
53
28
52
29
51
30
50
31
49
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AIN5
AIN4
AIN3
AGND
CAPC2
AGND
CML
REFOUT
AVDD
CAPY2
CAPY1
AGND
AIN2
AIN1
DGND
NC