TDA9550 PHILIPS [NXP Semiconductors], TDA9550 Datasheet - Page 66

• Manufacturer Part Number: TDA9550
• Description: TV signal processor-Teletext decoder with embedded m-Controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
RGB output circuit and black-current stabilization
In the RGB control circuit the signal is controlled on
contrast, brightness and saturation. The ICs have a linear
input for external RGB/YUV signals. Switching between
RGB and the YUV/YP
YUV0/YUV1 bits in subaddress 2BH. The signals for OSD
and text are internally supplied to the control circuit. The
output signal has an amplitude of about 2 V black-to-white
at nominal input signals and nominal settings of the
various controls.
To obtain an accurate biasing of the picture tube the
‘Continuous Cathode Calibration’ system has been
included in these ICs.
A black level off-set can be made with respect to the level
which is generated by the black current stabilization
system. In this way different colour temperatures can be
obtained for the bright and the dark part of the picture.
In the V
stabilization system checks the output level of the 3
channels and indicates whether the black level of the
highest output is in a certain window (WBC-bit) or below or
above this window (HBC-bit). This indication can be read
from the status byte 01 and can be used for automatic
adjustment of the V
TV receiver. During this test the vertical scan remains
active so that the indication of the 2 bits can be made
visible on the TV screen.
The control circuit contains a beam current limiting circuit
and a peak white limiting circuit. The peak white level is
adjustable via the I
limiting circuit reacts on the high frequency content of the
video signal a low-pass filter is inserted in front of the peak
detector. The circuit also contains a soft-clipper which
prevents that the high frequency peaks in the output signal
become too high. The difference between the peak white
limiting level and the soft clipping level is adjustable via the
I
During switch-off of the TV receiver a fixed beam current
is generated by the black current control circuit. This
current ensures that the picture tube capacitance is
discharged. During the switch-off period the vertical
deflection can be placed in an overscan position so that
the discharge is not visible on the screen.
A wide blanking pulse can be activated in the RGB outputs
by means of the HBL bit in subaddress 2BH. The timing of
this blanking can be adjusted by means of the bits WBF/R
bits in subaddress 03H.
2000 Jun 22
2
C-bus in a few steps.
TV signal processor-Teletext decoder with
embedded -Controller
g2
adjustment mode (AVG = 1) the black current
2
g2
C-bus. To prevent that the peak white
voltage during the production of the
R
P
B
mode can be realised via the
66
SOFTWARE CONTROL
The CPU communicates with the peripheral functions
using Special function Registers (SFRs) which are
addressed as RAM locations. The registers for the
Teletext decoder appear as normal SFRs in the
functions by using a serial bus. This bus is controlled by
dedicated hardware which uses a simple handshake
system for software synchronisation.
For compatibility reasons and possible re-use of software
blocks, the I
organised as in the stand-alone TV signal processors. The
TV processor registers cannot be read, so when the
content of these registers is needed in the software, a copy
should be stored in Auxiliary RAM or Non Volatile RAM.
The slave address of the TV signal processor is given in
Fig.28.
Valid subaddresses: 03H to 2EH, subaddress FE and FF
are reserved for test purposes. Auto-increment mode
available for subaddresses.
handbook, halfpage
-Controller memory map and are written to these
TDA955X/6X/8X PS/N1 series
A6
1
2
C-bus control for the TV processor is
Fig.28 Slave address (8A).
A5
0
A4
0
A3
0
Tentative Device Specification
A2
1
A1
0
A0
1
MLA743
R/W
1/0