M48T512Y-85PM1 STMICROELECTRONICS [STMicroelectronics], M48T512Y-85PM1 Datasheet - Page 9

• Manufacturer Part Number: M48T512Y-85PM1
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48T512Y, M48T512V
2.2
Figure 5.
Figure 6.
A0-A18
E
W
DQ0-DQ7
A0-A18
E
W
DQ0-DQ7
WRITE mode
The M48T512Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are low state after the address inputs are stable.
The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE
is terminated by the earlier rising edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for a minimum of t
t
must be valid t
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on W will disable the outputs t
falls.
WRITE AC waveforms, WRITE enable controlled
WRITE AC waveforms, chip enable controlled
WHAX
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in
DVWH
tAVEL
tAVWL
tAVEL
tAVWL
prior to the end of WRITE and remain valid for t
tWLQZ
Doc ID 5747 Rev 6
tAVEH
tAVWH
tWLWH
VALID
tAVAV
VALID
tAVAV
tELEH
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
tEHDX
EHAX
tWHQX
tEHAX
WHDX
tWHAX
from chip enable or
Operating modes
afterward. G
WLQZ
after W
AI02386
AI02387
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