PCF88332DA PHILIPS [NXP Semiconductors], PCF88332DA Datasheet - Page 89

• Manufacturer Part Number: PCF88332DA
• Description: STN RGB - 132 X 132 X 3 driver
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
15.7
Table 96 shows the sequence of commands to fill the OTP matrix as defined in Table 93.
Table 96 Sequence for filling the OTP matrix
Notes
1. X = don’t care. For hexadecimal representation, don’t care bits are assumed to be logic 0.
2. The chip stays in shift operation as long as D/C is logic 1.
15.8
In order to program an OTP cell, the associated register must be set to logic 1 and a programming voltage of 8 V should
to be applied to pins V
Table 97 to program the OTP cells. In any event the requirements stated in Section 15.9 must be met.
Important: Whenever a new row in the OTP matrix is selected (change of ORA[2:0]), the OTP cells must not be
connected to pin V
2003 Feb 14
1
2
3
4
shift15
shift14
shift13
shift12
shift11
shift10
shift9
shift8
shift7
shift6
shift5
shift4
shift3
shift2
shift1
shift0
5
STN RGB - 132
STEP
Example of filling the shift register
Programming flow
D/C
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
OTP(drain)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
0
1
1
1
OTP(gate)
X
X
X
X
X
X
X
X
X
X
6
0
1
1
0
0
0
0
0
0
0
0
1
(set OPE = 0). For an example see steps 9 to 11 in Table 97.
132
and V
5
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
COMMAND BYTE
OTP(drain)
3 driver
4
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
for 50 ms. It is strongly recommended to use the sequence shown in
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
(1)
X
X
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
89
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
ADDR
F0H
F1H
1AH
F0H
01H
01H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
07H
11H
00H
reset (may also be hardware
reset)
wait 1 ms for refresh to take
effect
enter CALMM mode
ORA = 000; OPE = 0;
CALMM = 1
send OTPSHTIN; note 2
set PVB[3:0]; BRS and TRS
set FVB[3:0]; 0 and EFD
set PVPR[8:3]
set PVPR[2:0] and FVPR[8:6]
set FVPR[5:0]
set SLD[2:0] and SLC[2:0]
set SLB[2:0] and SLA[2:0]
set PS[1:0]; FS[1:0] and ID3[7:6]
set ID3[5:0] and ID2[7]
set ID2[6:0]
set DF8[6:0]
set DFD[6:0]
set DFC[6:0]
set DFB[6:0]
set DFA[6:0]
set MMVOP[5:0] and SEAL
exit CALMM mode; if required
ORA = 000; OPE = 0;
CALMM = 0
DESCRIPTION
Objective specification
PCF8833