PCF8531U NXP [NXP Semiconductors], PCF8531U Datasheet - Page 20

• Manufacturer Part Number: PCF8531U
• Description: 34 x 128 pixel matrix driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8531_4
Product data sheet
9.2.2 V
9.3 Set Y address
9.4 Set X address
9.5 Set multiplex rate
9.6 Display control (D, E and IM)
9.7 Set bias system
When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as
shown in
into the DDRAM as shown in
Y address is 5.
Bits Y2, Y1 and Y0 define the Y address vector of the display RAM (see
Table 6.
The X address points to the columns. The range of X is 0 to 127 (7Fh).
M[1:0] selects the multiplex rate (see
Table 7.
Bits D and E select the display mode (see
to icon mode.
Different multiplex rates require different bias settings. Bias settings are programmed by
BS[2:0], which sets the binary number n. The optimum value for n is given by:
Supported values of n are given in
n
Y2
0
0
0
0
1
1
Multiplex rate
1:17
1:26
1:34
•
=
Register settings remain unchanged
muxrate 3
Figure
Y address
Multiplex rates
–
10. When V = 1 the vertical addressing is selected. The data is written
Y1
0
0
1
1
0
0
Rev. 04 — 13 June 2008
Figure
M1
0
1
0
Table
9. Icon data is written independently of V when
Table
8.
Table
7).
Table 9
Y0
0
1
0
1
0
1
13). Bit IM (see
shows the intermediate bias voltages.
M0
0
0
1
34 x 128 pixel matrix driver
Table
Bank
0
1
2
3
4
5 (icons)
12) sets the display
PCF8531
© NXP B.V. 2008. All rights reserved.
Table
6).
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