PCF8531U NXP [NXP Semiconductors], PCF8531U Datasheet - Page 17
PCF8531U
Manufacturer Part Number
PCF8531U
Description
34 x 128 pixel matrix driver
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF8531U.pdf
(44 pages)
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NXP Semiconductors
PCF8531_4
Product data sheet
Fig 7.
DDRAM to display data mapping
8.1 Addressing
Data is written in bytes into the RAM matrix of the PCF8531 as shown in
Figure 9
addressed by the address pointer. The address ranges are X 0 to X 127 (7Fh) and Y 0 to
Y 5 (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode
(V = 1), the Y address increments after each byte (see
(Y = 4), Y wraps around to 0 and X increments to address the next column. In horizontal
addressing mode (V = 0), the X address increments after each byte (see
the last X address (X = 127), X wraps around to 0 and Y increments to address the next
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
and
Figure
DDRAM
10. The display RAM has a matrix of 34
Rev. 04 — 13 June 2008
mgs468
LCD
R33 (icon row)
R32
R24
R16
Figure
34 x 128 pixel matrix driver
9). After the last Y address
128 bits. The columns are
top of LCD
R8
R0
PCF8531
© NXP B.V. 2008. All rights reserved.
Figure
Figure
10). After
8,
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