ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 22

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

ADF4150HV
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of the
MOD phase offsets with respect to the input reference, where
MOD is the fractional modulus. The phase resync feature of
the
respect to the input reference. This is necessary in applications
where the output phase and frequency are important, such as
digital beamforming. For information about how to program
a specific RF output phase when using phase resync, see the
Phase Programmability section.
Phase resync is enabled by setting Bits[DB16:DB15] in
Register 3 to 10. When phase resync is enabled, an internal
timer generates sync signals at intervals of t
following formula:
where:
CLK_DIV_VALUE is the decimal value programmed in
Bits[DB14:DB3] of Register 3 and can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bits[DB14:DB3]
of Register 1.
t
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The t
a value that is at least as long as the worst-case lock time. This
guarantees that the phase resync occurs after the last cycle slip
in the PLL settling transient.
PFD
ADF4150HV
is the PFD reference period.
t
SYNC
= CLK_DIV_VALUE × MOD × t
produces a consistent output phase offset with
SYNC
time must be programmed to
PFD
SYNC
given by the
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In the example shown in Figure 27, the PFD reference is 25 MHz
and MOD is 125 for a 200 kHz channel spacing. t
400 μs by programming CLK_DIV_VALUE = 80.
Phase Programmability
The phase word in Register 1 controls the RF output phase. As
this word is swept from 0 to MOD, the RF output phase sweeps
over a 360° range in steps of 360°/MOD.
FREQUENCY
(INTERNAL)
PHASE
SYNC
LE
–100
LAST CYCLE SLIP
0
Figure 27. Phase Resync Example
100
200
INCORRECT PHASE
300
PLL SETTLES TO
t
SYNC
400
TIME (µs)
500
600
CORRECT PHASE
PLL SETTLES TO
AFTER RESYNC
700
800
SYNC
is set to
900
1000