ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 11

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. The SW1 and
SW2 switches are normally closed. The SW3 switch is normally
open. When power-down is initiated, SW3 is closed, and SW1
and SW2 are opened. In this way, no loading of the REF
occurs during power-down.
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. The division ratio is determined by the INT, FRAC, and
MOD values, which build up this divider (see Figure 15).
INT, FRAC, MOD, and R Counter Relationship
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the PFD frequency. For more informa-
tion, see the RF Synthesizer—A Worked Example section.
The RF VCO frequency (RF
where:
RF
oscillator (VCO).
RF Divider is the output divider that divides down the VCO
frequency.
INT is the preset divide ratio of the binary 16-bit counter (23 to
32,767 for the 4/5 prescaler, 75 to 65,535 for the 8/9 prescaler).
FRAC is the numerator of the fractional division (0 to MOD − 1).
MOD is the preset fractional modulus (2 to 4095).
OUTPUT DIVIDERS
OUT
RF
VCO OUTPUT/
is the output frequency of the external voltage controlled
OUT
REF
= (f
FROM
IN
PFD
NC
POWER-DOWN
/RF Divider) × [INT + (FRAC/MOD)]
SW1
RF N DIVIDER
Figure 14. Reference Input Stage
CONTROL
N COUNTER
NO
VALUE
Figure 15. RF N Divider
INT
NC
SW3
SW2
OUT
100kΩ
) equation is
BUFFER
VALUE
MOD
N = INT + FRAC/MOD
INTERPOLATOR
THIRD-ORDER
FRACTIONAL
TO R COUNTER
VALUE
FRAC
IN
TO PFD
pin
Rev. 0 | Page 11 of 28
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The PFD frequency (f
where:
REF
D is the REF
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REF
Integer-N Mode
If FRAC = 0 and the DB8 (LDF) bit in Register 2 is set to 1,
the synthesizer operates in integer-N mode. The DB8 bit in
Register 2 should be set to 1 for integer-N digital lock detect.
R Counter
The 10-bit R counter allows the input reference frequency
(REF
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND HIGH
VOLTAGE CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the
R counter and N counter and produces an output proportional
to the phase and frequency difference between them. Figure 16
is a simplified schematic of the phase frequency detector.
The PFD includes a delay element that sets the width of the
antibacklash pulse to 4.2 ns. This pulse ensures that there is
no dead zone in the PFD transfer function and provides a
consistent reference spur level.
The high voltage charge pump is designed on an Analog
Devices, Inc., proprietary high voltage process and allows the
charge pump to output voltages as high as 29 V when powered
by a 30 V supply. The high voltage charge pump removes the
need for active filtering when interfacing to a high voltage VCO.
IN
+IN
–IN
f
IN
HIGH
HIGH
PFD
is the reference input frequency.
) to be divided down to produce the reference clock
= REF
IN
IN
D2
D1
divide-by-2 bit (0 or 1).
doubler bit.
IN
CLR1
CLR2
U1
U2
× [(1 + D)/(R × (1 + T))]
Figure 16. PFD Simplified Schematic
Q1
Q2
PFD
UP
DOWN
DELAY
) equation is
U3
CHARGE
PUMP
ADF4150HV
CP
OUT
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