ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 12

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

ADF4150HV
MUXOUT AND LOCK DETECT
The multiplexer output on the
access various internal points on the chip. The state of MUXOUT is
controlled by the M3, M2, and M1 bits in Register 2 (see Figure 22).
Figure 17 shows the MUXOUT section in block diagram form.
INPUT SHIFT REGISTERS
The
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. As shown in Figure 2, the control bits are the three LSBs:
DB2, DB1, and DB0. The truth table for these bits is shown in
Table 6. Figure 19 summarizes how the latches are programmed.
Table 6. Truth Table for C3, C2, and C1 Control Bits
C3
0
0
0
0
1
1
ANALOG LOCK DETECT
THREE-STATE-OUTPUT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
ADF4150HV
Control Bits
RESERVED
C2
0
0
1
1
0
0
DV
GND
DD
digital section includes a 10-bit RF R counter,
Figure 17. MUXOUT Schematic
C1
0
1
0
1
0
1
MUX
R COUNTER INPUT
ADF4150HV
CONTROL
Register
Register 0 (R0)
Register 1 (R1)
Register 2 (R2)
Register 3 (R3)
Register 4 (R4)
Register 5 (R5)
allows the user to
DV
GND
DD
MUXOUT
Rev. 0 | Page 12 of 28
PROGRAM MODES
Table 6 and Figure 19 through Figure 25 show how the program
modes are set up in the ADF4150HV.
The following settings in the
phase value, modulus value, reference doubler, reference divide-
by-2, R counter value, and charge pump current setting. Before
the part uses a new value for any double-buffered setting, the
following two events must occur:
1.
2.
For example, any time that the modulus value is updated,
Register 0 (R0) must be written to, to ensure that the modulus
value is loaded correctly. The divider select value in Register 4
(R4) is also double buffered, but only if the DB13 bit of
Register 2 (R2) is high.
OUTPUT STAGE
The RF
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 18. To allow the user to
optimize the power dissipation vs. output power requirements,
the tail current of the differential pair is programmable using
Bits[DB4:DB3] in Register 4 (R4). Four current levels can be set.
These levels give output power levels of −4 dBm, −1 dBm, +2 dBm,
and +5 dBm, respectively, using a 50 Ω resistor to AV
coupling into a 50 Ω load. Alternatively, both outputs can be
combined in a 1 + 1:1 transformer or a 180° microstrip coupler
(see the Output Matching section). If the outputs are used
individually, the optimum output stage consists of a shunt
inductor to AV
Another feature of the
the RF output stage can be shut down until the part achieves lock,
as measured by the digital lock detect circuitry. This feature is
enabled by the mute-till-lock detect (MTLD) bit in Register 4 (R4).
The new value is latched into the device by writing to the
appropriate register.
A new write is performed on Register 0 (R0).
VCO
OUT
+ and RF
DD
DIVIDE-BY-1/-2/-4/-8/-16
.
OUT
BUFFER/
Figure 18. Output Stage
ADF4150HV
− pins of the
ADF4150HV
ADF4150HV
is that the supply current to
RF
OUT
+
are double buffered:
RF
OUT
are connected
–
DD
and ac