ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 21

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

SPURIOUS OPTIMIZATION AND BOOST MODE
Narrow loop bandwidths can filter unwanted spurious signals,
but these bandwidths usually have a long lock time. A wider
loop bandwidth achieves faster lock times, but may lead to
increased spurious signals inside the loop bandwidth.
The boost mode feature can achieve the same fast lock time
as the wider bandwidth, but with the advantage of a narrow
final loop bandwidth to keep spurs low (see the Boost Enable
section).
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4150HV.
Fractional Spurs
The fractional interpolator in the
Σ-Δ modulator with a modulus (MOD) that is programmable to
any integer value from 2 to 4095. In low spur mode (dither on),
the minimum allowable value of MOD is 50. The Σ-Δ modulator
is clocked at the PFD reference rate (f
put frequencies to be synthesized at a channel step resolution
of f
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is f
in the digital Σ-Δ modulator. For the third-order Σ-Δ modulator
used in the ADF4150HV, the repeat length depends on the value
of MOD, as listed in Table 8.
Table 8. Fractional Spurs with Dither Off (Low Noise Mode)
MOD Value (Dither Off)
MOD is divisible by 2, but not by 3
MOD is divisible by 3, but not by 2
MOD is divisible by 6
MOD is not divisible by 2, 3, or 6
In low spur mode (dither on), the repeat length is extended
to 2
quantization error spectrum look like broadband noise. This
may degrade the in-band phase noise at the PLL output by as
much as 10 dB. For lowest noise, dither off is a better choice,
particularly when the final loop bandwidth is low enough to
attenuate even the lowest frequency fractional spur.
PFD
21
cycles, regardless of the value of MOD, which makes the
/MOD.
PFD
/L, where L is the repeat length of the code sequence
ADF4150HV
PFD
Repeat
Length
2 × MOD
3 × MOD
6 × MOD
MOD
), which allows PLL out-
is a third-order
Spur Interval
Channel step/2
Channel step/3
Channel step/6
Channel step
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Integer Boundary Spurs
Another mechanism for fractional spur creation is the inter-
actions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related (the
purpose of a fractional-N synthesizer), spur sidebands appear
on the VCO output spectrum at an offset frequency that corre-
sponds to the beat note, or difference frequency, between an
integer multiple of the reference and the VCO frequency. These
spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus the
name integer boundary spurs).
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop may cause a problem. The PCB layout must
ensure adequate isolation between VCO traces and the input
reference to avoid a possible feedthrough path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantiza-
tion noise of the Σ-Δ modulator also depends on the particular
phase word with which the modulator is seeded.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
lookup table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4150HV.
If a lookup table is not used, keep the phase word at a constant
value to ensure consistent spur levels on any particular frequency.
ADF4150HV