PCA2125TS NXP [NXP Semiconductors], PCA2125TS Datasheet - Page 16

• Manufacturer Part Number: PCA2125TS
• Description: SPI Real-time clock/calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA2125_1
Product data sheet
If a new value of n is written before the end of the current timer period, then this value will
take immediate effect. NXP Semiconductors does not recommend changing n without first
disabling the counter (by setting bit TE = 0). The update of n is asynchronous with the
timer clock, therefore changing it without setting bit TE = 0 will result in a corrupted value
loaded into the countdown counter which results in an undetermined countdown period for
the first period. The countdown value n will however be correctly stored and correctly
loaded on subsequent timer periods.
When the countdown timer flag is set, an interrupt signal on INT will be generated
provided that this mode is enabled. See
be controlled.
When starting the timer for the first time, the first period will have an uncertainty which is a
result of the enable instruction being generated from the interface clock which is
asynchronous with the timer source clock. Subsequent timer periods will have no such
delay. The amount of delay for the first timer period will depend on the chosen source
clock; see
Table 29.
At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF can
only be cleared by software. The asserted bit TF can be used to generate an interrupt
(INT). The interrupt can be generated as a pulsed signal every countdown period or as a
permanently active signal which follows the condition of bit TF. Bit TI_TP is used to control
this mode selection and the interrupt output can be disabled with bit TIE.
Timer source clock
4096 Hz
64 Hz
1 Hz
1
Fig 10. General countdown timer behavior
60
countdown value, n
countdown counter
timer source clock
Hz
In the example it is assumed that the timer flag is cleared before the next countdown period expires
and that the INT is set to pulsed mode.
Table
First period delay for timer counter value n
INT
TE
TF
29.
xx
xx
Rev. 01 — 28 July 2008
03
03
Minimum timer period
n
n
(n 1) +
(n 1) +
1
1
64
64
Section 8.7.2
02
Hz
Hz
duration of first timer period after
enable may range from n
01
03
for details on how the interrupt can
02
n
SPI Real-time clock/calendar
Maximum timer period
n + 1
n + 1
n +
n +
01
1
1
1 to n + 1
64
64
Hz
Hz
03
PCA2125
© NXP B.V. 2008. All rights reserved.
02
n
01
001aaf906
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03