PCA2125TS NXP [NXP Semiconductors], PCA2125TS Datasheet - Page 14

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PCA2125TS

Manufacturer Part Number
PCA2125TS
Description
SPI Real-time clock/calendar
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PCA2125_1
Product data sheet
Table 26.
The minute and second flag (bit MSF) is set to logic 1 when either the seconds or the
minutes counter increments according to the currently enabled interrupt. The flag can be
read and cleared by the interface. The status of bit MSF does not affect the INT pulse
generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT
pulse will still be generated.
The purpose of the flag is to allow the controlling system to interrogate the PCA2125 and
identify the source of the interrupt such as the minute/second or countdown timer.
Minute interrupt (bit MI)
0
1
0
1
Fig 9.
seconds counter
seconds counter
minutes counter
minutes counter
a. INT and MSF when SI enabled (MSF flag not cleared after an interrupt)
b. INT and MSF when only MI enabled
Bit TI_TP is set to logic 1 resulting in
INT example for bits SI and MI
MSF
MSF
Effect of bits MI and SI on INT generation
INT
INT
58
58
59
59
Rev. 01 — 28 July 2008
Second interrupt (bit SI) Result
0
0
1
1
1
64
Hz wide interrupt pulse.
59
11
59
11
00
12
00
12
no interrupt generated
an interrupt once per minute
an interrupt once per second
an interrupt once per second
SPI Real-time clock/calendar
PCA2125
00
00
© NXP B.V. 2008. All rights reserved.
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