CY7C1480BV25-167AXI CYPRESS [Cypress Semiconductor], CY7C1480BV25-167AXI Datasheet - Page 23

• Manufacturer Part Number: CY7C1480BV25-167AXI
• Description: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Timing for the write cycle is shown in
Note
Document #: 001-15143 Rev. *D
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
BW
ADV
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t CL
(continued)
t DS
Single WRITE
D(A1)
t ADH
t DH
Figure
A2
7.
[19, 20]
Figure 7. Write Cycle Timing
D(A2)
DON’T CARE
D(A2 + 1)
t WES
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
X
LOW.
ADV suspends burst
CY7C1482BV25, CY7C1486BV25
D(A2 + 2)
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
CY7C1480BV25
t
ADVS
t WES
Extended BURST WRITE
D(A3 + 1)
t
t WEH
ADVH
Page 23 of 31
D(A3 + 2)
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