CY7C1480BV25-167AXI CYPRESS [Cypress Semiconductor], CY7C1480BV25-167AXI Datasheet - Page 22

• Manufacturer Part Number: CY7C1480BV25-167AXI
• Description: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Timing for the read cycle is shown in
Document #: 001-15143 Rev. *D
Note
19. On this diagram, when CE is LOW: CE
Data Out (Q)
GW, BWE,
ADDRESS
ADSP
ADSC
BWx
ADV
CLK
OE
CE
t
ADS
t AS
t CES
A1
t
ADH
t AH
t CEH
t
CH
High-Z
t CYC
t WES
t
CL
Single READ
t CLZ
t WEH
t CO
1
is LOW, CE
Figure
t ADS
A2
Q(A1)
t ADH
t OEHZ
6.
2
is HIGH, and CE
[19]
t ADVS
Figure 6. Read Cycle Timing
t ADVH
t OELZ
t OEV
Q(A2)
DON’T CARE
3
t DOH
is LOW. When CE is HIGH: CE
t CO
Q(A2 + 1)
ADV
suspends
burst.
UNDEFINED
CY7C1482BV25, CY7C1486BV25
Q(A2 + 2)
BURST READ
1
is HIGH, CE
Q(A2 + 3)
2
is LOW, or CE
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
CY7C1480BV25
3
is HIGH.
Q(A2 + 1)
t CHZ
Deselect
cycle
Page 22 of 31
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