CY7C1354C CYPRESS [Cypress Semiconductor], CY7C1354C Datasheet - Page 6

• Manufacturer Part Number: CY7C1354C
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05538 Rev. *G
Pin Definitions
A0, A1
A
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
DQ
DQP
MODE
TDO
TDI
TMS
TCK
V
V
V
DD
DDQ
SS
Pin Name
1
2
3
S
a
c
,BW
,BW
X
b
d
,
,
I/O Power Supply Power supply for the I/O circuitry.
JTAG serial input
Test Mode Select
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
JTAG-Clock
JTAG serial
I/O Type
Ground
output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
I/O-
I/O-
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a Write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQP
BW
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Clock input to the JTAG circuitry.
Ground for the device. Should be connected to ground of the system.
2
1
c
c
and CE
, and DQP
and CE
controls DQ
1
and CE
2
3
to select/deselect the device.
to select/deselect the device.
d
is controlled by BW
3
c
and DQP
to select/deselect the device.
a
is controlled by BW
c
a
, BW
–DQ
d
d
controls DQ
are placed in a tri-state condition. The outputs are automat-
d
.
Pin Description
a
controls DQ
a
, DQP
d
and DQP
b
is controlled by BW
a
and DQP
d
.
a
, BW
b
controls DQ
b
, DQP
CY7C1354C
CY7C1356C
c
is controlled by
Page 6 of 28
b
[a:d].
and DQP
During
b
,
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