CY7C1354C CYPRESS [Cypress Semiconductor], CY7C1354C Datasheet
CY7C1354C
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CY7C1354C Summary of contents
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... Pipelined SRAM with NoBL™ Architecture Functional Description The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states ...
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... ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT E REGISTER 1 READ LOGIC Sleep Control 250 MHz 200 MHz 2.8 3.2 250 220 40 40 CY7C1354C CY7C1356C ...
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... DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ NC DQa 28 53 DQa DQPa CY7C1354C CY7C1356C DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa ...
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... DDQ DDQ DDQ NC/144M T NC/72M U V DDQ Document #: 38-05538 Rev. *G 119-Ball BGA Pinout CY7C1354C (256K × 36 NC/18M ADV/ DQP ...
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... V b DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document #: 38-05538 Rev. *G 165-Ball FBGA Pinout CY7C1354C (256K × 36 CEN CLK ...
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... The outputs are automat controlled DQP controlled CY7C1354C CY7C1356C and DQP , BW controls DQ and DQP and DQP . d During [a:d]. is controlled DQP is controlled by ...
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... Document #: 38-05538 Rev. *G Pin Description Burst Read Accesses The CY7C1354C and CY7C1356C have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above ...
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... Because the CY7C1354C and CY7C1356C are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to (DQ /DQP for CY7C1354C and DQ a,b,c,d a,b,c,d CY7C1356C) inputs. Doing so will tri-state the output drivers. ...
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... Truth Table Operation NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SLEEP MODE Partial Write Cycle Description Function (CY7C1354C) Read Write –No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354C/CY7C1356C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance ...
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... CK and CK# captured in the boundary scan register. Once the data is captured possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. CY7C1354C CY7C1356C Unlike the SAMPLE/PRELOAD ...
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... Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [10, 11] Over the Operating Range Description / ns CY7C1354C CY7C1356C TDOV Min. Max. Unit MHz ...
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... V = 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1356C 000 000 01011001000010110 Reserved for future use. 00000110100 Allows unique identification of SRAM vendor CY7C1354C CY7C1356C to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 0.3 ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05538 Rev. *G Bit Size (x36) Bit Size (x18 Description CY7C1354C CY7C1356C Page [+] Feedback [+] Feedback ...
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... K10 63 L10 64 M10 65 J11 66 K11 67 L11 68 M11 69 N11 R11 R10 P10 CY7C1354C CY7C1356C (continued) 119-ball ID 165-ball Not Bonded Not Bonded (Preset to 1) (Preset ...
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... Not Bonded 63 (Preset R11 65 R10 P10 CY7C1354C CY7C1356C (continued) 119-ball ID 165-ball Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded ...
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... V ≤ /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1354C CY7C1356C + 0.5V DD Ambient Temperature DDQ 0°C to +70°C 3.3V –5%/+10% 2.5V – Min. Max. Unit 3.135 3.6 3 ...
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... OUTPUT GND 351Ω INCLUDING JIG AND SCOPE ( 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1354C CY7C1356C 119 BGA 165 FBGA Max. Max. Unit 119 BGA 165 FBGA Max. Max. ...
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... V minimum initially, before a Read or Write operation can 2.5V. DDQ and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1354C CY7C1356C –200 –166 Min. Max. Min. Max. Unit 1 1 ...
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... DOH CLZ D(A1) D(A2) Q(A3) D(A2+1) BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1354C CY7C1356C OEV CHZ Q(A4) Q(A4+1) D(A5) t OEHZ t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...
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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Document #: 38-05538 Rev. *G [23, 24, 26 D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE CY7C1354C CY7C1356C CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED ...
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... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05538 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1354C CY7C1356C Page [+] Feedback [+] Feedback ...
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... CY7C1354C-200AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1356C-200AXC CY7C1354C-200BGC 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1356C-200BGC CY7C1354C-200BGXC 51-85115 119-ball Ball Grid Array ( 2.4 mm) Lead-Free CY7C1356C-200BGXC CY7C1354C-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1356C-200BZC CY7C1354C-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array ( ...
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... CY7C1354C-250AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1356C-250AXC CY7C1354C-250BGC 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1356C-250BGC CY7C1354C-250BGXC 51-85115 119-ball Ball Grid Array ( 2.4 mm) Lead-Free CY7C1356C-250BGXC CY7C1354C-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1356C-250BZC CY7C1354C-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array ( ...
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... JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1354C CY7C1356C 1.40±0.05 12°±1° A SEE DETAIL (8X) 0 ...
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... 0.70 REF. 12.00 30° TYP. SEATING PLANE C Document #: 38-05538 Rev. *G Ø1.00(3X) REF 0.15(4X) CY7C1354C CY7C1356C Ø0. Ø0. Ø0.75±0.15(119X 1.27 3 ...
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... SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC CY7C1354C CY7C1356C BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø ...
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... Document History Page Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05538 REV. ECN No. Issue Date ** 242032 See ECN *A 278130 See ECN *B 284431 See ECN *C 320834 See ECN *D 351895 See ECN *E 377095 See ECN ...